W83627F Information Storage Devices, Inc, W83627F Datasheet - Page 80

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W83627F

Manufacturer Part Number
W83627F
Description
LPC Interface I/o Plus Kbc, Game Port, Midi Port
Manufacturer
Information Storage Devices, Inc
Datasheet

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CR26 (Default 0b0s000000)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
: SEL4FDD
= 0
= 1
These two bits define how to enable Configuration mode. The corresponding power-on
setting pin is NRTSA (pin 51).
HEFRAS Address and Value
= 0 Write 87h to the location 2E twice.
= 1 Write 87h to the location 4Etwice.
: LOCKREG
= 0 Enable R/W Configuration Registers
= 1 Disable R/W Configuration Registers.
:Reserve
: DSFDLGRQ
= 0 Enable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is
= 1 Disable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is not
: DSPRLGRQ
= 0
= 1
: DSUALGRQ
= 0
= 1
: DSUBLGRQ
= 0
= 1
: HEFRAS
Disable UART A legacy mode IRQ selecting, then MCR bit 3 is not effective on
Select two FDD mode.
Select four FDD mode.
Enable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is effective on
Disable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is not effective
Enable UART A legacy mode IRQ selecting, then MCR bit 3 is effective on
Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective on
effective on selecting IRQ
on selecting IRQ
selecting IRQ
selecting IRQ
Enable UART B legacy mode IRQ selecting, then MCR bit 3 is effective on selecting
IRQ
effective on selecting IRQ
selecting IRQ
selectingIRQ
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Publication Release Date:November 2002
W83627HF/F
Revision 2.0

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