r2j20604np Renesas Electronics Corporation., r2j20604np Datasheet - Page 11

• Manufacturer Part Number: r2j20604np
• Description: Integrated Driver - Mos Fet Drmos
• Manufacturer: Renesas Electronics Corporation.

R2J20604NP
The PWM input is TTL level and has hysteresis. When the PWM input signal is abnormal, e.g., when the signal route
from the control IC is abnormal, the tri-state function turns off the high- and low-side MOS FETs. This function
operates when the PWM input signal stays in the input hysteresis window for 240 ns (typ.). After the tri-state mode has
been entered and GH and GL have become low, a PWM input voltage of 2.1 V or more is required to make the circuit
return to normal operation.
For the high-side driver, the BOOT pin is the power-supply voltage pin and voltage VSWH provides a standard for
operation of the high-side driving circuit. Consequently, the difference between the voltage on the BOOT and VSWH
pins becomes the gate swing for the high-side MOS FET. Connect a bootstrap capacitor between the BOOT pin and the
VSWH pin. Since the Schottky barrier diode (SBD) is connected between the BOOT and Reg5V pins, this bootstrap
capacitor is charged up to 5 V. When the high-side MOS FET is turned on, voltage VSWH becomes equal to VIN, so
VBOOT is boosted to VSWH + 5 V.
The GH and GL pins are the gate-monitor pins for each MOS FET.
MOS FETs
The MOS FETs incorporated in R2J20604NP are highly suitable for synchronous-rectification buck conversion. For
the high-side MOS FET, the drain is connected to the VIN pin and the source is connected to the VSWH pin. For the
low-side MOS FET, the drain is connected to the VSWH pin and the source is connected to the PGND pin.
REJ03G1605-0200 Rev.2.00 Jun 30, 2008
Page 11 of 14
PWM
GH
GL
PWM
GH
GL
2.1 V
1.2 V
2.1 V
1.2 V
240 ns(t
240 ns(t
HOLD-OFF
HOLD-OFF
Figure 1
)
)
240 ns(t
240 ns(t
HOLD-OFF
HOLD-OFF
)
)