hip6019cb Intersil Corporation, hip6019cb Datasheet - Page 13

• Manufacturer Part Number: hip6019cb
• Description: Advanced Dual Pwm And Dual Linear Power Control
• Manufacturer: Intersil Corporation

equations give the approximate response time interval for
application and removal of a transient load:
where: I
response time to the application of load, and t
response time to the removal of load. With a +5V input source,
the worst case response time can be either at the application or
removal of load and dependent upon the output voltage setting.
Be sure to check both of these equations at the minimum and
maximum output levels for the worst case response time.
Input Capacitor Selection
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline.
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use ceramic capacitance
for the high frequency decoupling and bulk capacitors to
supply the RMS current. Small ceramic capacitors should be
placed very close to the upper MOSFET to suppress the
voltage induced in the parasitic circuit impedances.
For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-
GX or equivalent) may be needed. For surface mount
designs, solid tantalum capacitors can be used, but caution
must be exercised with regard to the capacitor surge current
rating. These capacitors must be capable of handling the
surge-current at power-up. The TPS series available from
AVX, and the 593D series from Sprague are both surge
current tested.
MOSFET Selection/Considerations
The HIP6019 requires 4 N-Channel power MOSFETs. Two
MOSFETs are used in the synchronous-rectified buck
topology of PWM1 converter. PWM2 converter uses a
MOSFET as the buck switch and the linear controller drives
a MOSFET as a pass transistor. These should be selected
based upon r
management requirements.
PWM1 MOSFET Selection and Considerations
In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes two
loss components; conduction loss and switching loss. These
losses are distributed between the upper and lower
MOSFETs according to duty factor (see the equations
below). The conduction losses are the only component of
t
RISE
=
TRAN
------------------------------- -
V
L
O
IN
–
DS(ON)
I
is the transient load current step, t
TRAN
V
OUT
, gate supply requirements, and thermal
2-264
t
FALL
=
L
------------------------------ -
O
V
OUT
I
TRAN
FALL
RISE
is the
is the
HIP6019
power dissipation for the lower MOSFETs. Only the upper
MOSFET has switching losses, since the lower device turns
on into near zero voltage.
The equations below assume linear voltage-current
transitions and do not model power loss due to the reverse-
recovery of the lower MOSFET’s body diode. The gate-
charge losses are proportional to the switching frequency
(F
contributing to the MOSFETs’ temperature rise. However,
large gate charge increases the switching interval, t
which increases the upper MOSFET switching losses.
Ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature by
calculating the temperature rise according to package
thermal resistance specifications. A separate heatsink may
be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
The r
if the type device is used for both. This is because the gate
drive applied to the upper MOSFET is different than the
lower MOSFET. Figure 14 shows the gate drive where the
upper gate-to-source voltage is approximately V
input supply. For +5V main power and +12V
the gate-to-source voltage of Q1 is 7V. The lower gate drive
voltage is +12V
for Q1 and a logic-level MOSFET can be used for Q2 if its
absolute gate-to-source voltage rating exceeds the
maximum voltage applied to V
Rectifier CR1 is a clamp that catches the negative inductor
swing during the dead time between the turn off of the
lower MOSFET and the turn on of the upper MOSFET. The
diode must be a Schottky type to prevent the lossy parasitic
MOSFET body diode from conducting. It is acceptable to
P
P
UPPER
LOWER
S
HIP6019
) and are dissipated by the HIP6019, thus not
-
+
DS(ON)
+12V
=
=
I
----------------------------------------------------------- -
I
-------------------------------------------------------------------------------- -
O
FIGURE 14. OUTPUT GATE DRIVERS
O
is different for the two previous equations even
2
2
DC
V
r
CC
r
DS ON
GND
DS ON
. A logic-level MOSFET is a good choice
UGATE
PHASE
LGATE
PGND
V
IN
V
IN
V
V
OUT
IN
CC
–
+
V
.
I
----------------------------------------------------
OUT
O
Q1
Q2
+5V OR LESS
V
IN
2
CR1
t
DC
SW
NOTE:
V
NOTE:
V
GS
GS
for the bias,
CC
F
V
S
SW
V
less the
CC
CC
-5V