a8438eej-t Allegro MicroSystems, Inc., a8438eej-t Datasheet - Page 14

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a8438eej-t

Manufacturer Part Number
a8438eej-t
Description
A8438 Photoflash Capacitor Charger With Igbt Driver
Manufacturer
Allegro MicroSystems, Inc.
Datasheet
A8438
Adjusting Output Voltage
The A8438 senses output voltage during switch off-time. This
allows the voltage divider network, R1 through R3 (see figure
6), to be connected at the anode of the high voltage output diode,
D1, eliminating power loss due to the feedback network when
charging is complete. The output voltage can be adjusted by
selecting proper values of the voltage divider resistors. Use the
following equation to calculate values for Rx (Ω):
least 300 V. A typical 1206 surface mount resistor has a 150 V
breakdown voltage rating. It is recommended that R1 and R2
have similar values to ensure an even voltage stress between
them. Recommended values are:
which together yield a stop voltage of 303 V.
offer significant efficiency improvement, because the power loss
of the feedback network occurs mainly during switch off-time,
and because the off-time is only a small fraction of each charging
cycle.
Output Diode Selection
Choose the rectifying diode(s), D1, to have small parasitic
capacitance (short reverse recovery time) while satisfying the
reverse voltage and forward current requirements.
The peak reverse voltage of the diode, V
Recommended Components Table
C1 Input Capacitor
C2 Input Capacitor
COUT Photoflash
Capacitor
D1, Output Diode
R1, R2, FB Resistors 150 kΩ,
R3, FB Resistor
T1, Transformer
R1 = R2 = 150 kΩ (1206)
R3 = 1.2 kΩ (0603)
R1 and R2 together need to have a breakdown voltage of at
Using higher resistance values for R1, R2, and R3 does not
Component
R
1
R
3
0.1 μF, ± 10%, 16 V X7R ceramic capacitor (0603)
4.7 μF, ± 10%, 10 V, X5R ceramic capacitor (0805)
330 V, 100 μF (or 19 to 180 μF)
2 x 250 V, 225 mA, 5 pF
2 x 300 V, 225 mA, 5 pF
1.20 kΩ
1:10, L
1:10.4, L
1:10, L
1:10, L
1:10, L
R
2
V
V
Primary
Primary
Primary
Primary
OUT
FB
1
1
Primary
/
/
4
10
W ± 1% (1206)
W ± 1% (0603)
= 10.8 μH, for I
= 8 μH, for I
= 14 μH, for I
1 .
= 7.4 μH, for I
= 4.7 μH, for I
D_Peak
Rating
, occurs when the
LIM
Photoflash Capacitor Charger with IGBT Driver
LIM
LIM
LIM
= 2.0 A
LIM
= 2.0 A
= 2.0 A
= 1.6 or 1.8 A
= 2.0 A
(4)
internal MOSFET switch is closed, and the primary-side current
starts to ramp-up. It can be calculated as:
The peak current of the rectifying diode, ID_Peak, is calculated
as :
Input Capacitor Selection
Ceramic capacitors with X5R or X7R dielectrics are recom-
mended for the input capacitor, C2. It should be rated at least
4.7 μF / 6.3 V to decouple the battery input, V
of the transformer. When using a separate bias, V
A8438 VIN supply, connect at least a 0.1 μF / 6.3 V bypass
capacitor to the VIN pin.
Layout Guidelines
Key to a good layout for the photoflash capacitor charger circuit
is to keep the parasitics minimized on the power switch loop
(transformer primary side) and the rectifier loop (secondary side).
Use short, thick traces for connections to the transformer primary
and SW pin.
Output voltage sensing circuit elements must be kept away from
switching nodes such as SW pin. Make sure that there is no GND
plane underneath R1 and R2, because parasitic capacitance to
ground will affect sensing accuracy. It is important that the
¯ N ¯ ¯ E ¯
switching traces, in order to minimize noise pickup. In addition,
high voltage isolation rules must be followed carefully to avoid
breakdown failure of the circuit board.
signal trace be routed away from the transformer and other
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V
Part Number
I
D _ Peak
D _ Peak
V
I
OUT
Primary_Peak
115 Northeast Cutoff, Box 15036
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
N
V
/
BATT
N
.
Murata
Taiyo Yuden
Chemi-Con
Philips Semiconductor,
Fairchild Semiconductor
Vishay
Yageo
Yageo
Asatech
TDK
TDK
Tokyo Coil Engineering
Tokyo Coil Engineering
.
BATT
Source
BIAS
, at the primary
, for the
(6)
(5)
¯ D ¯ ¯ O ¯
14

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