an30181a Panasonic Corporation of North America, an30181a Datasheet - Page 14

• Manufacturer Part Number: an30181a
• Description: General-purpose Power Management Lsi
• Manufacturer: Panasonic Corporation of North America

AN30181A
1. Start / Stop sequence (continued)
Technical Data (continued)
The operation of each block is as follows.
UVLO function
Reset function
DCDC1 (Output voltage : 1.2 V)
External Pch-MOSFET gate control function
External synchronization signal output function
DCDC2 (Output voltage : 1.8 V)
BUF (Output voltage : 0.9 V)
When power supply rises to 2.6 V or higher at EN = High, UVLO is released, and the operation of each function starts.
Since this function's hysteresis is 100 mV, UVLO detects when power supply falls to 2.5 V or lower, then each function shuts
down.
RESET pin shifts to High at 30 ms delay after power supply rises to 2.92 V or higher.
(Output type : Nch MOS open drain)
Since this function's hysteresis is 110 mV, RESET pin shifts to Low when power supply falls to 2.81 V or lower.
(No delay in case of High → Low)
When UVLO is released, DCDC1 starts and outputs 1.2 V. Soft-start function operates for 1 ms after startup. Since output
voltage rises slowly, limiting input current, it is possible to prevent rush current and overshoot.
When UVLO detects, DCDC1 turns off. When EN pin shifts to Low, an output pin (FB1) is terminated with a resistor.
PCNT pin is discharged by the constant current (2.5 μA) at 3.75 ms delay after UVLO is released.
By connecting the gate of Pch MOSFET to PCNT pin, it is possible to turn on this FET softly.
At the same time, the termination with a resistor of DIS pin is released.
Just after UVLO detects, PCNT pin voltage becomes V
PCNTB pin outputs the signal which synchronized with the above-mentioned PCNT pin. Therefore, PCNTB pin outputs High
at 3.75 ms delay after UVLO is released. PCNTB pin outputs Low just after UVLO detects.
DCDC2 starts and outputs 1.8 V at 7.5 ms delay after UVLO is released. DCDC2 has the same soft-start function as DCDC1
and starts, preventing rush current and overshoot.
DCDC2 stops because UVLO detects. When EN pin shifts to Low, an output pin (FB2) is terminated with a resistor.
BUF pin outputs 0.9 V at 8.5 ms delay after UVLO is released. BUF starts, preventing rush current and overshoot.
BUF stops because UVLO detects. BUF is terminated with a resistor when EN pin shifts to Low.
IN
Ver. AEB
and DIS pin is terminated with a resistor.
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