x9523v20iz-bt1 Intersil Corporation, x9523v20iz-bt1 Datasheet - Page 11

• Manufacturer Part Number: x9523v20iz-bt1
• Description: Dual Dcp, Por, Dual Voltage Monitors
• Manufacturer: Intersil Corporation

POR1, POR0: Power-on Reset bits - (Nonvolatile)
Applying voltage to V
circuit which holds V1RO output HIGH, until the supply
voltage stabilizes above the V
period of time, t
The Power-on Reset bits, POR1 and POR0 of the
CONSTAT register determine the tPURST delay time of
the Power-on Reset circuitry (See "VOLTAGE MONI-
TORING FUNCTIONS"). These bits of the CONSTAT
register are nonvolatile, and therefore power-up to the
last written state.
The nominal Power-on Reset delay time can be selected
from the following table, by writing the appropriate bits to
the CONSTAT register:
The default for these bits are POR1 = 0, POR0 = 1.
V2OS, V3OS: Voltage Monitor Status Bits (Volatile)
Bits V2OS and V3OS of the CONSTAT register are
latched, volatile flag bits which indicate the status of the
Voltage Monitor reset output pins V2RO and V3RO.
At power-up the VxOS (x = 2,3) bits default to the value
“0”. These bits can be set to a “1” by writing the appropri-
ate value to the CONSTAT register. To provide consis-
tency between the VxRO and VxOS however, the status
of the VxOS bits can only be set to a “1” when the corre-
sponding VxRO output is HIGH.
SCL
SDA
POR1
0
0
1
1
S
T
A
R
T
POR0
1
0
1
0
1
SLAVE ADDRESS BYTE
PURST
0
1
Power-on Reset delay (t
(See Figure 25).
CC
0
activates the Power-on Reset
Figure 13. CONSTAT Register Write Command Sequence
0
11
100ms (Default)
1
TRIP1
200ms
300ms
0
50ms
R/W A
threshold for a
C
K
PUV1RO
1
1
ADDRESS BYTE
)
1
X9523
1
1
1
Once the VxOS bits have been set to “1”, they will be
reset to “0” if:
—The device is powered down, then back up,
—The corresponding VxRO output becomes LOW.
CONSTAT Register Write Operation
The CONSTAT register is accessed using the Slave
Address set to 1010010 (Refer to Figure 4.). Following
the Slave Address Byte, access to the CONSTAT regis-
ter requires an Address Byte which must be set to FFh.
Only one data byte is allowed to be written for each
CONSTAT register Write operation. The user must issue
a STOP, after sending this byte to the register, to initiate
the nonvolatile cycle that stores the DWLK, POR1 and
POR0 bits. The X9523 will not ACKNOWLEDGE any
data bytes written after the first byte is entered (Refer to
Figure 13.).
When writing to the CONSTAT register, the bit CS4 must
always be set to “0”. Writing a “1” to bit CS4 of the CON-
STAT register is a reserved operation.
Prior to writing to the CONSTAT register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps
—Write a 02H to the CONSTAT Register to set the Write
—Write a 06H to the CONSTAT Register to set the Reg-
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded
by a START and ended with a STOP).
ister Write Enable Latch (RWEL) AND the WEL bit.
This is also a volatile cycle. The zeros in the data byte
are required. (Operation preceded by a START and
ended with a STOP).
1
1
A
C
K
CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0
CONSTAT REGISTER DATA IN
A
C
K
January 3, 2006
S
T
O
P
FN8209.1