lm5045sqx National Semiconductor Corporation, lm5045sqx Datasheet - Page 4

• Manufacturer Part Number: lm5045sqx
• Description: Full-bridge Pwm Controller With Integrated Mosfet Drivers
• Manufacturer: National Semiconductor Corporation

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TSSOP
Pin
10
11
12
13
14
15
3
4
5
6
7
8
9
LLP Pin
27
28
10
11
1
2
3
4
5
6
7
8
9
RT/SYNC Oscillator Frequency Control and
SLOPE
SSOFF
RAMP
COMP
AGND
Name
SSSR
RES
REF
RD1
RD2
CS
SS
Input to PWM Comparator
Current Sense Input
Slope Compensation Current
Input to the Pulse Width Modulator An external opto-coupler connected to the COMP pin sources
Output of a 5V reference
Frequency Synchronization
Analog Ground
Synchronous Rectifier Leading
Edge Delay
Synchronous Rectifier Trailing
Edge Delay
Restart Timer
Soft-Start Input
Secondary Side Soft-Start
Soft-Stop Disable
Description
4
Modulation ramp for the PWM comparator. This ramp can be a
signal representative of the primary current (current mode) or
proportional to the input voltage (feed-forward voltage mode).
This pin is reset to GND at the end of every cycle.
If CS exceeds 750mV the PWM output pulse will be terminated,
entering cycle-by-cycle current limit. An internal switch holds CS
low for 40nS after either output switches high to blank leading
edge transients.
A ramping current source from 0 to 100µA is provided for slope
compensation in current mode control. This pin can be connected
through an appropriate resistor to the CS pin to provide slope
compensation. If slope compensation is not required, SLOPE
must be tied to ground.
current into an internal NPN current mirror. The PWM duty cycle
is at maximum with zero input current, while 1mA reduces the
duty cycle to zero. The current mirror improves the frequency
response by reducing the AC voltage across the opto-coupler.
Maximum output current is 15mA. Locally decouple with a 0.1µF
capacitor.
The resistance connected between RT and AGND sets the
oscillator frequency. Synchronization is achieved by AC coupling
a pulse to the RT/SYNC pin that raises the voltage at least 1.5V
above the 2V nominal bias level.
Connect directly to the Power Ground.
The resistance connected between RD1 and AGND sets the
delay from the falling edge of SR1 or SR2 and the rising edge of
HO2/LO1 or HO1/LO2 respectively.
The resistance connected between RD2 and AGND sets the
delay from the falling edge of HO1/LO2 or HO2/LO1 and the rising
edge of SR2 or SR1 respectively.
Whenever the CS pin exceeds the 750mV cycle-cycle current
limit threshold, 30µA current is sourced into the RES capacitor for
the remainder of the PWM cycle. If the RES capacitor voltage
reaches 1.0V, the SS capacitor is discharged to disable the HO1,
HO2, LO1, LO2 and SR1, SR2 outputs. The SS pin is held low
until the voltage on the RES capacitor has been ramped between
2V and 4V eight times by 10µA charge and 5µA discharge
currents. After the delay sequence, the SS capacitor is released
to initiate a normal start-up sequence.
An internal 20µA current source charges the SS pin during start-
up. The input to the PWM comparator gradually rises as the SS
capacitor charges to steadily increase the PWM duty cycle.
Pulling the SS pin to a voltage below 200mV stops PWM pulses
at HO1,2 and LO1,2 and turns off the synchronous rectifier FETs
to a low state.
An external capacitor and an internal 20µA current source set the
soft-start ramp for the synchronous rectifiers. The SSSR
capacitor charge-up is enabled after the first output pulse and
SS>2V and Icomp <800µA
When SS OFF pin is connected to the AGND, the LM5045 soft-
stops in the event of a VIN UVLO and Hiccup mode current limit
condition. If the SSOFF pin is connected to REF pin, the controller
hard-stops on any fault condition. Refer Table 1 for more details.
Application Information