lm5022mme National Semiconductor Corporation, lm5022mme Datasheet - Page 18

• Manufacturer Part Number: lm5022mme
• Description: 60v Low Side Controller For Boost And Sepic
• Manufacturer: National Semiconductor Corporation

www.national.com
MOSFET SWITCHING LOSS
P
MOSFET AND R
OUTPUT DIODE LOSS
The average output diode current is equal to I
estimated forward drop, V
therefore:
INPUT CAPACITOR LOSS
This term represents the loss as input ripple current passes
through the ESR of the input capacitor bank. In this equation
‘n’ is the number of capacitors in parallel. The 4.7 µF input
capacitors selected have a combined ESR of approximately
1.5 mΩ, and Δi
OUTPUT CAPACITOR LOSS
This term is calculated using the same method as the input
capacitor loss, substituting the output capacitor RMS current
for V
approximately 1.5 mΩ.
BOOST INDUCTOR LOSS
The typical DCR of the selected inductor is 40 mΩ.
SW
IN
= 0.5 x 13.8 x 1.5 x (10 ns + 12 ns) x 5 x 10
P
= 13.8V. The output capacitors' combined ESR is also
CIN
P
I
O-RMS
C
I
IN-RMS
= [0.16
P
= 0.66 x (1.5
P
Q
P
P
C
= 13.8 X (3.5m + 13.5m) = 235 mW
SW
CO
= D x (I
L
= 1.13 x 1.5 x (0.66 x 0.34)
for a 13.8V input is 0.55A:
= 0.29 x Δi
SNS
= 0.5 x V
2
= [0.8 x 0.0015] / 2 = 0.6 mW
P
x 0.0015] / 2 = 0.02 mW (negligible)
D1
CONDUCTION LOSS
P
= 0.5 x 0.5 = 0.25W
L
DCR
2
P
2
x (R
D1
x (0.029 + 0.1)) = 192 mW
D
IN
, is 0.5V. The output diode loss is
= I
L
= I
x I
DSON
= 0.29 x 0.55 = 0.16A
L
O
2
L
x DCR
x V
x (t
x 1.3 + R
D
R
+ t
F
FIGURE 11. Boost Converter Current Loops
) x f
0.5
SNS
SW
= 0.8A
O
, or 0.5A. The
))
5
= 114 mW
18
Core loss in the inductor is estimated to be equal to the DCR
loss, adding an additional 90 mW to the total inductor loss.
TOTAL LOSS
EFFICIENCY
Layout Considerations
To produce an optimal power solution with the LM5022, good
layout and design of the PCB are as important as the com-
ponent selection. The following are several guidelines to aid
in creating a good layout.
FILTER CAPACITORS
The low-value ceramic filter capacitors are most effective
when the inductance of the current loops that they filter is
minimized. Place C
GND pins of the LM5022. Place C
C
SENSE LINES
The top of R
separate trace made as short as possible. Route this trace
away from the inductor and the switch node (where D1, Q1,
and L1 connect). For the voltage loop, keep R
the LM5022 and run a trace from as close as possible to the
positive side of C
should be routed away from the inductor and the switch node.
These measures minimize the length of high impedance lines
and reduce noise pickup.
COMPACT LAYOUT
Parasitic inductance can be reduced by keeping the power
path components close together and keeping the area of the
loops that high currents travel small. Short, thick traces or
copper pours (shapes) are best. In particular, the switch node
should be just large enough to connect all the components
together without excessive heating from the current it carries.
The LM5022 (boost converter) operates in two distinct cycles
whose high current paths are shown in Figure 11:
F
next to the VCC and GND pins of the LM5022.
P
LOSS
SNS
= Sum of All Loss Terms = 972 mW
P
η = 20 / (20 + 0.972) = 95%
should be connected to the CS pin with a
OX
DCR
INX
to R
= 1.5
as close as possible to the VIN and
FB2
2
. As with the CS line, the FB line
x 0.04 = 90 mW
20212252
OX
close to the load, and
FB1/2
close to