ncp5890 ON Semiconductor, ncp5890 Datasheet - Page 8

• Manufacturer Part Number: ncp5890
• Description: Light Management Ic Dedicated For Lcd Backlighting And Multi-led Fun Light Applications
• Manufacturer: ON Semiconductor

I2CADR = Low ³ address = %0111 0010 = $72
I2CADR = High ³ address = %0111 0100 = $74
level at the I2CADR pin must be hardwired either to GND
or to Vbat prior to power up the system.
($72 or $74) when a Write is send to the chip.
sent by the MCU. The frame contains three consecutive
bytes and shall fulfill the I2C specifications (see Figure 6):
Read operation, care must be observed since sending a
Read command ($73 or $75) is equivalent to a Write
command and the selected register will be updated
accordingly.
Registers Setup Selection
frame and must be followed by the DATA register. The
SCL
SDA
Table 2. Register Selection Code
0A
0B
0C
0D
0E
0F
00
01
02
03
04
05
06
07
08
09
In order to avoid any risk during the operation, the digital
The first byte of the I2C frame shall be selected address
To set up a new output current value, a full frame will be
On the other hand, although the chip does not handle the
The register selection follows the I2C address of a new
$
Start Conditions
SCL
SDA
B7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I2C Address
B6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B7
B6
B5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B5
I2C Address
B4
Register Selection
B4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B3
B2
B3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B1
B0
Figure 6. Single Frame I2C Sequence
B2
Figure 7. Multi Frames I2C Sequence
ACK
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B7
B1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
B6
DATA
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B5
Register Selection
B0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
B4
B3
8
Shut Down the chip
Select I−LED current setup and immediate LED update
Set ILED target and Gradual Dimming UPWARD
Set ILED target and Gradual Dimming DOWNWD
Set timing and start the gradual dimming
Select PWM0 register
Select PWM1 register
Select PWM2 register
Set up Photo sense input stage gain
Set up Photo Sense I−LED minimum value
Set up Photo Sense up/down timing
RFU
RFU
RFU
RFU
Reserved for manufacturing test: do not access
N sequences
B2
− First byte: I2C address, write ³ $72
− Second byte: register selection ³ %0000 0000 =
− Third byte: DATA ³ %0000 0000 = function / output
send on the I2C port once the physical address has been
decoded (see Figure 7). The transmission ends when the
STOP signal is send by the SCL/SDA digital code.
content of the register selection byte is not stored into the
chip and a new one must be sent for every DATA update.
The low nibble contains the selected register number as
depicted in Table 2. The high nibble is reserved for future
use.
control the manufacturing test and access to this register is not
permitted outside the ON Semiconductor final test facilities.
An infinite number of register selection / data pair can be
The last code $0F is reserved for ON Semiconductor to
(assuming I2CADR = Low)
internal register address
current value
B1
B0
ACK
B7
Register Selection
B6
B5
B4
DATA
B3
B2
B1
B0
DATA
ACK
Stop conditions