ncp5358 ON Semiconductor, ncp5358 Datasheet - Page 9

• Manufacturer Part Number: ncp5358
• Description: Gate Driver For Desktop Power Systems
• Manufacturer: ON Semiconductor

each phase designed for driving two N−channel MOSFETs
in a synchronous buck converter topology. This driver is
compatible with the Signal channel NCP5359 gate drive.
This gate drives has a Bi−direction fault detection and
multi−level PWM input feature. When the gate driver works
with ON’s NCP539X controller, it can provide a difference
output logic status through multi−level PWM input. For this
new feature, higher efficiency can be provided. For the
bi−direction fault detection function, it is used to provide a
driver state information to other gate drivers and controller
in a multi−phase buck converter. e.g over voltage protection
(OVP) function at startup, thermal shutdown and under
voltage lockout (UVLO). This feature can provide an
additional protection function for the multi−phase system
when the fault condition occurs in one channel. With this
additional feature, converter overall system will be more
reliable and safe.
Enable Pin
drain MOSFET. This pin is controlled by internal or external
signal. There are three conditions will be triggered:
pull low. In this case, both channel drive output DRVH and
DRVL will be forced low, until the fault mode remove then
restart automatic.
Under Voltage Lockout
until V
signals will control the gate status when V
exceeded. If V
output gate will be forced low until input voltage V
above the startup threshold.
The NCP5358 gate driver is a dual phase MOSFET driver,
The bi−direction enable pin is connected with an open
When the internal fault has been detected, EN pin will be
The DRVH1, DRVH2 and DRVL1, DRVL2 are held low
1. The voltage at SW1 or SW2 pin is higher than
2. The controller hits the UVLO at V
3. The controller hits the thermal shutdown.
CC
preset voltage at power start up.
pin.
or V
CC
CCP
decreases to 3.2 V below the threshold, the
reaches 9 V during startup. The PWM
CC
CC
pin or V
threshold is
CC
http://onsemi.com
CCP
rises
9
Power ON Reset
abnormal status driving the start up condition. When the
initial soft start voltage V
driver will monitor the switching node SW pin. If SW1 or
SW2 pin high than 1.9 V, bottom gate will be force to high
for discharge the output capacitor. The fault mode will be
latch and EN pin will force both channel to be low, unless the
driver is recycle. When input voltage is higher than 9 V, the
gate driver will normal operation, top gate driver DRVH and
bottom gate driver will follow the PWM signal decode to a
status.
Adaptive Non−overlap
shoot through damage the power MOSFETs. When the
PWM signal pull high, DRVL will go low after a
propagation delay, the controller will monitors the switching
node (SW) pin voltage and the gate voltage of the MOSFET
to know the status of the MOSFET. When the low side
MOSFET status is off an internal timer will delay turn on of
the high−side MOSFET. When the PWM pull low, gate
DRVH will go low after the propagation delay (tpdDRVH).
The time to turn off the high side MOSFET is depending on
the total gate charge of the high−side MOSFET. A timer will
be triggered once the high side MOSFET is turn off to delay
the turn on the low−side MOSFET.
Layout Guidelines
converter. Bootstrap capacitor and V
critical items, it should be placed as close as to the driver IC.
Another item is using a GND plane. Ground plane can
provide a good return path for gate drives for reducing the
ground noise. Therefore GND pin should be directly
connected to the ground plane and close to the low−side
MOSFET source pin in every channel. Also, the gate drive
trace should be considered. The gate drives has a high di/dt
when switching, therefore a minimized gate drives trace can
reduce the di/dv, raise and fall time for reduce the switching
loss.
Power on reset feature is used to protect a gate driver avoid
The non−overlap dead time control is used to avoid the
Layout is very important thing for design a DC−DC
CC
is higher than 3.2 V, the gate
CC
capacitor are most