ncp1560hdr2g ON Semiconductor, ncp1560hdr2g Datasheet - Page 17

• Manufacturer Part Number: ncp1560hdr2g
• Description: Full Featured Voltage Mode Pwm Controller
• Manufacturer: ON Semiconductor

7.0 V before the converter output is completely in regulation
causing the outputs to be disabled. If the converter output is
not completely discharged when the outputs are reenabled,
the converter will eventually reach regulation exhibiting a
nonmonotonic startup behavior. But, if the converter output
is completely discharged when the outputs are reenabled, the
cycle may repeat and the converter will not start.
capacitor is discharged. Once the fault is removed, a
soft−start cycle commences. The soft−start steady state
voltage is approximately 4.1 V.
Control Outputs
and OUT2, with adjustable overlap delay (t
precedes OUT1 during a low to high transition and OUT1
precedes OUT2 at any high to low transition. Figure 35
shows the relationship between OUT1 and OUT2.
Output 2, once inverted, can control a synchronous rectifier.
The overlap delay prevents simultaneous conduction.
Output 2 can also be used to control an active clamp reset.
disabled and the One Shot Pulse Generator is enabled. If no
faults are present, the outputs turn ON. Otherwise, the
outputs remain OFF until the fault is removed and V
reaches 11 V again.
can supply up to 10 mA each and their high state voltage is
usually 0.2 V below V
voltage should not exceed the maximum input voltage of the
driver stage.
If the soft−start period is too long, V
In the event of an UV, OV, or cycle skip fault, the soft−start
The NCP1560 has two in−phase control outputs, OUT1
Generally, OUT1 controls the main switching element.
Once V
The control outputs are biased from V
Figure 35. Control Outputs Timing Diagram
t
D
(Leading)
AUX
OUT1
OUT2
reaches 11 V, the internal startup circuit is
AUX
. Therefore, the auxiliary supply
t
D
(Trailing)
AUX
AUX
may discharge to
. The outputs
D
). OUT2
http://onsemi.com
AUX
17
a driver should be used between the NCP1560 and the load.
ON Semiconductor’s MC33152 is a good selection for an
integrated driver. Figures 27 and 28 shows the relationship
between the output’s rise and fall times vs capacitive load.
Time Delay
a resistor (R
delay of 80 ns is obtained when R
is obtained by increasing R
current of the time delay circuit is reduced, increasing its
noise susceptibility. If a delay higher than 150 ns is required,
it is recommended to place a small capacitor between the t
pin and ground.
selecting appropriate values of R
be noted that the overlap delay may cause OUT2 to reach
100% duty cycle. Therefore, if OUT2 is used, the maximum
duty cycle of OUT2 needs to be kept below 100%. The
maximum overlap delay, t
duty cycle and frequency of operation. The maximum
overlap delay is calculated using the equation below.
300 kHz with a maximum duty cycle of 80%, the maximum
allowed overlap delay is 333 ns. However, this is a
theoretical limit and variations over the complete operating
range should be considered when selecting the overlap
delay.
Additional Information
designed and implemented using the NCP1560. The
converter delivers 100 W at 3.3 V and achieves a full load
efficiency of 85%. The system is built using a 4 layer FR4,
single sided board. The components location within the
board is shown in Figure 36 and the complete circuit
schematic is shown in Figure 37. The converter design is
discussed in Application Note AND8105/D. Please contact
your sales representative for board availability.
If the control outputs need to drive a large capacitive load,
The overlap delay between the outputs is set connecting
The output duty cycle can be adjusted from 0% to 85%
For example, if the converter operates at a frequency of
A 100 W DC−DC converter for telecom systems is
D
) between the t
t D(max) v
D(max)
D
D
(1 * DC)
. As R
and V
, depends on the maximum
D
FF
2
is 60 kW. A higher delay
ƒ
and V
D
REF
increases, the bias
pins. An overlap
DC(inv)
. It should
D