sg6741a Fairchild Semiconductor, sg6741a Datasheet - Page 8

• Manufacturer Part Number: sg6741a
• Description: Sg6741a ? Highly Integrated Green-mode Pwm Controller
• Manufacturer: Fairchild Semiconductor

© 2008 Fairchild Semiconductor Corporation
SG6741A • Rev. 1.0.1
Functional Description
Startup Current
For startup, the HV pin is connected to the line input or
bulk capacitor through an external resistor, R
is recommended as 100KΩ. Typical startup current
drawn from pin HV is 2mA and charges the hold-up
capacitor through the resistor R
capacitor level reaches V
switches off. At this moment, the V
supplies the SG6741A to maintain V
auxiliary winding of the main transformer provides the
operating current.
Operating Current
Operating current is around 4mA. The low operating
current enables a better efficiency and reduces the
requirement of V
Green-Mode Operation
The proprietary green-mode function provides an off-
time modulation to reduce the switching frequency in
the light-load and no-load conditions. The on-time is
limited for better abnormal or brownout protection. V
which is derived from the voltage feedback loop, is
taken as the reference. Once V
threshold voltage, switching frequency is continuously
decreased to the minimum green-mode frequency
around 18KHz (R
Oscillator Operation
A resistor connected from the RI pin to the GND pin
generates a constant current source for the controller.
This current is used to determine the center PWM
frequency. Increasing the resistance reduces PWM
frequency. Using a 26KΩ resistor R
corresponding 65KHz PWM frequency. The relationship
between R
The range of the PWM oscillation frequency is designed
as 47kHz ~ 109kHz.
Current Sensing and PWM Current
Limiting
Peak-current-mode control is utilized in SG6741A to
regulate output voltage and provide pulse-by-pulse
current limiting. The switch current is detected by a
sense resistor into the SENSE pin. The PWM duty cycle
is determined by this current sense signal and V
feedback voltage. When the voltage on the SENSE pin
reaches around V
terminates immediately. V
variable voltage around 0.85V for output power limit.
f
PWM
=
I R
I
1690
and the switching frequency is:
(K
Ω
DD
)
I
=26KΩ).
(KHz)
COMP
hold-up capacitance
= (V
COMP
DD-ON
FB
–1.2)/3.2, a switch cycle
is internally clamped to a
, the startup current
FB
HV
. When the V
is lower than the
DD
.
I
DD
capacitor only
results in a
before the
HV
, which
FB
, the
(1)
FB
DD
,
8
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on
spike occurs on the sense-resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period, the
current-limit comparator is disabled and cannot switch
off the gate driver.
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally
at 16.5V and 10.5V. During startup, the hold-up
capacitor must be charged to 16.5V through the startup
resistor to enable the IC. The hold-up capacitor
continues to supply V
delivered from auxiliary winding of the main transformer.
V
UVLO hysteresis window ensures that hold-up capacitor
is adequate to supply V
Gate Output / Soft Driving
The BiCMOS output stage is a fast totem-pole gate
driver. Cross conduction is avoided to minimize heat
dissipation, increase efficiency, and enhance reliability.
The output driver is clamped by an internal 18V Zener
diode to protect power MOSFET transistors against
undesirable gate over voltage. A soft driving waveform
is implemented to minimize EMI.
Built-in Slope Compensation
The sensed voltage across the current-sense resistor is
used for peak-current-mode control and pulse-by-pulse
current limiting. Built-in slope compensation improves
stability or prevents sub-harmonic oscillation. SG6741A
inserts a synchronized positive-going ramp at every
switching cycle.
Constant Output Power Limit
When the SENSE voltage, across the sense resistor R
reaches the threshold voltage, around 0.9V, the output
GATE drive is turned off after a small delay, t
delay introduces an additional current proportional to t
• V
of the input voltage V
larger additional current and the output power limit is
higher than that under low input line voltage. To
compensate this variation for wide AC input range, a
sawtooth power-limiter is designed to solve the unequal
power-limit problem. The power limiter is designed as a
positive ramp signal fed to the inverting input of the
OCP comparator. This results in a lower current limit at
high-line inputs than at low-line inputs.
DD
IN
must not drop below 10.5V during startup. This
/ L
P
. Since the delay is nearly constant, regardless
IN,
DD
DD
higher input voltage results in a
during startup.
before the energy can be
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PD
. This
PD
s
,