nsbmc290 National Semiconductor Corporation, nsbmc290 Datasheet - Page 5

• Manufacturer Part Number: nsbmc290
• Description: Burst Mode Memory Controller
• Manufacturer: National Semiconductor Corporation

A(A B)0 – 10
RAS(A B)
CAS(A B)0-3
MWE(A B)
DBLE(A B)
DBTX(A B)
IBTX(A B)
Pin Descriptions
MEMORY INTERFACE
The NSBMC290 is designed to drive a memory array orga-
nized as 2 banks each of 32 bits The address and control
signals for the memory array are output through high current
BUFFER CONTROLS
In order not to limit system implementation strategies vis j
vis instruction and data bus organization the NSBMC290
permits the designer to keep these busses separate or not
Pin
Pin
Data Bus Latch Enable A and B (Output Active High) These outputs are used to enable transparent latches to
latch data from the Processor data bus to each bank of memory during a write cycle (Data access only)
The following buffer control outputs are multi-mode signals The signal names as they appear on the logic symbol
are the default signal names (Mode
Data Bus Transmit A and B (Output Active Low) These outputs are used during read cycles to enable data
from the individual banks of memory to drive the data bus
Instruction Bus Transmit A and B (Output Active Low) These outputs are used during instruction cycles to
enable data from the individual banks of memory to drive the instruction bus
Multiplexed Addresses (Output High Current) These two buses transfer the multiplexed row and column
addresses to the memory array banks A and B respectively
Row Address Strobes (Output High Current Active Low) These signals are strobes that indicate the
existence of a valid row address on A(A B)0 – 10 These signals are to be connected to the two interleaved banks
of memory One is assigned to each bank
Column Address Strobe (Output High Current Active Low) These signals are strobes that indicate a valid
column address on A(A B)0 – 10 A set of each of these (A B) are assigned to each memory bank and within each
set one is assigned to each byte of the 32-bit memory
Memory Write Enable (Output High Current Active Low) These signals are the write strobes for the DRAM
memories One is supplied for each of the two banks of memory although they are logically identical
(Continued)
e
0) A more complete description is presented in the configuration section
5
Description
Description
drivers in order to minimize the propagation delay due to
memory input impedance and trace capacitance External
array drivers are not required The address and control sig-
nals however must be externally terminated
as performance criteria dictate In order to maintain bus
separation data buffers are required In order to maximize
performance these buffers are controlled directly by the
NSBMC290