xcf08s Xilinx Corp., xcf08s Datasheet
xcf08s
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xcf08s Summary of contents
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R DS123 (v2.15) July 07, 2008 Features • In-System Programmable PROMs for Configuration of ® Xilinx FPGAs • Low-Power Advanced CMOS NOR Flash Process • Endurance of 20,000 Program/Erase Cycles • Operation over Full Industrial Temperature Range (–40°C to +85°C) ...
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R X-Ref Target - Figure 1 CLK TCK Control TMS and JTAG TDI Interface TDO CF Figure 1: XCFxxS Platform Flash PROM Block Diagram X-Ref Target - Figure 2FI CLK CE OSC Control TCK and TMS TDI JTAG TDO Interface ...
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R Table 2: Xilinx FPGAs and Compatible Platform Flash PROMs Configuration FPGA Platform Flash PROM Bitstream ® Virtex -5 LX FPGAs XC5VLX30 8,374,016 XC5VLX50 12,556,672 XC5VLX85 21,845,632 XC5VLX110 29,124,608 XC5VLX155 41,048,064 XC5VLX220 53,139,456 XC5VLX330 79,704,832 XCF32P+XCF32P+XCF16P Virtex-5 LXT FPGAs XC5VLX20T ...
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R Table 2: Xilinx FPGAs and Compatible Platform Flash PROMs (Cont’d) Configuration FPGA Platform Flash PROM Bitstream Virtex-E FPGAs XCV50E 630,048 XCV100E 863,840 XCV200E 1,442,016 XCV300E 1,875,648 XCV400E 2,693,440 XCV405E 3,430,400 XCV600E 3,961,632 XCV812E 6,519,648 XCV1000E 6,587,520 XCV1600E 8,308,992 XCV2000E ...
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R Programming The Platform Flash PROM is a reprogrammable NOR flash device (refer "Quality and Reliability Characteristics," page 28 for the program/erase specifications). Reprogramming requires an erase followed by a program operation. A verify operation is recommended after the program ...
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R Design Security The Xilinx in-system programmable Platform Flash PROM devices incorporate advanced data security features to fully protect the FPGA programming data against unauthorized reading via JTAG. The XCFxxP PROMs can also be programmed to prevent inadvertent writing via ...
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R IEEE 1149.1 Boundary-Scan (JTAG) The Platform Flash PROM family is compatible with the IEEE 1149.1 Boundary-Scan standard and the IEEE 1532 in- system configuration standard. A Test Access Port (TAP) and registers are provided to support all required Boundary-Scan ...
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R Table 7: XCFxxS Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence IR[7:5] TDI → Reserved Table 8: XCFxxP Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence IR[15:9] IR[8:7] TDI ...
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R Platform Flash PROM TAP Characteristics The Platform Flash PROM family performs both in-system programming and IEEE 1149.1 Boundary-Scan (JTAG) testing via a single 4-wire Test Access Port (TAP). This simplifies system designs and allows standard Automatic Test Equipment to ...
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R Additional Features for the XCFxxP Internal Oscillator The 8/16/32 Mbit XCFxxP Platform Flash PROMs include an optional internal oscillator which can be used to drive the CLKOUT and DATA pins on FPGA configuration interface. The internal oscillator can be ...
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two separate design revisions: one 16-Mbit design revision, one 8-Mbit design revision, or two 8-Mbit design revisions. • A single 8-Mbit PROM can store only one 8-Mbit design revision. Larger design revisions can be split over several ...
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R X-Ref Target - Figure 5 PROM 0 REV 0 (8 Mbits) REV 1 (8 Mbits) REV 2 (8 Mbits) REV 3 (8 Mbits) 4 Design Revisions (a) Design Revision storage examples for a single XCF32P PROM PROM 0 REV ...
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R PROM to FPGA Configuration Mode and Connections Summary The FPGA's I/O, logical functions, and internal interconnections are established by the configuration data contained in the FPGA’s bitstream. The bitstream is loaded into the FPGA either automatically upon power up, ...
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R Serial Daisy Chain Multiple FPGAs can be daisy-chained for serial configuration from a single source. After a particular FPGA has been configured, the data for the next device is routed internally to the FPGA’s DOUT pin. Typically the data ...
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R CCLK. If BUSY is asserted (High) by the FPGA, the configuration data must be held until BUSY goes Low. The FPGA's active-Low Chip Select (CS or CS_B) and active-Low Write (WRITE or RDWR_B) signals must be tied to ground ...
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R Initiating FPGA Configuration The options for initiating FPGA configuration via the Platform Flash PROM include: • Automatic configuration on power up • Applying an external PROG_B (or PROGRAM) pulse • Applying the JTAG CONFIG instruction Following the FPGA’s power-on ...
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R Configuration PROM-to-FPGA Device Interface Connection Diagrams X-Ref Target - Figure CCJ CCO CCINT V CCINT (2) V CCO (2) V CCJ Platform Flash PROM OE/RESET TDI TDI TMS TMS TCK TCK TDO GND Notes: 1 ...
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R X-Ref Target - Figure 7 (3) External Oscillator CCJ CCO CCINT V CCINT (2) V CCO (2) V CCJ Platform Flash PROM OE/RESET TDI TDI TMS TMS TCK TCK TDO GND Notes: 1 For Mode pin ...
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R X-Ref Target - Figure CCJ CCO CCINT CCJ V D0 CCINT (2) V CCO (2) V CCJ Platform Flash PROM Cascaded CLK PROM CE (PROM 1) CEO OE/RESET (3) TDI TDI CF TMS TMS ...
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R X-Ref Target - Figure CCJ CCO CCINT V CCINT (2) V CCO (2) V CCJ XCFxxP Platform Flash PROM OE/RESET TDI TDI TMS TMS BUSY TCK TCK TDO GND Notes: 1 For Mode pin connections ...
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R X-Ref Target - Figure 10 External Oscillator CCJ CCO CCINT V CCINT (2) V CCO (2) V CCJ XCFxxP Platform Flash PROM OE/RESET TDI TDI TMS TMS BUSY TCK TCK TDO GND Notes: 1 For Mode ...
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R X-Ref Target - Figure CCJ CCO CCINT CCJ D[0:7] V CCINT CCO (2) V CCJ (2) V XCFxxP Platform Flash PROM Cascaded CLK PROM CE (PROM 1) CEO OE/RESET (4) TDI TDI CF (3) ...
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R X-Ref Target - Figure CCJ CCO CCINT CCJ External Oscillator V D0 CCINT CCO (2) V CCJ (2) V XCFxxP Platform Flash PROM Cascaded CLK PROM CE (PROM 1) CEO OE/RESET (3) TDI CF ...
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R X-Ref Target - Figure CCJ CCO CCINT CCJ External Oscillator V D[0:7] CCINT CCO (2) V CCJ (2) V XCFxxP Platform Flash PROM Cascaded CLK PROM CE (PROM 1) CEO OE/RESET (4) TDI ...
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R Reset and Power-On Reset Activation At power up, the device requires the V monotonically rise to the nominal operating voltage within the specified V rise time. If the power supply cannot CCINT meet this requirement, then the device might ...
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R Standby Mode The PROM enters a low-power standby mode whenever CE is deasserted (High). In standby mode, the address counter is reset, CEO is driven High, and the remaining outputs are placed in a high-impedance state regardless of the ...
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R DC Electrical Characteristics Absolute Maximum Ratings Symbol Description V Internal supply voltage relative to GND CCINT V I/O supply voltage relative to GND CCO V JTAG I/O supply voltage relative to GND CCJ V Input voltage with respect to ...
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R Recommended Operating Conditions Symbol Description V Internal voltage supply CCINT V 3.3V Operation CCO Supply voltage 2.5V Operation for output 1.8V Operation drivers 1.5V Operation V Supply voltage 3.3V Operation CCJ for JTAG output 2.5V Operation drivers V 3.3V ...
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R DC Characteristics Over Operating Conditions Symbol Description High-level output voltage for 3.3V outputs High-level output voltage for 2.5V outputs V OH High-level output voltage for 1.8V outputs High-level output voltage for 1.5V outputs Low-level output voltage for 3.3V outputs ...
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R AC Electrical Characteristics AC Characteristics Over Operating Conditions XCFxxS and XCFxxP PROM as Configuration Slave with CLK Input Pin as Clock Source X-Ref Target - Figure 15 T SCE CE OE/RESET CLK BUSY T OE (optional DATA ...
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R Symbol Description (6) Clock period (serial mode) when V (6) Clock period (serial mode) when V T CYC (6) Clock period (parallel mode) when V (6) Clock period (parallel mode) when V (3) CLK Low time when V T ...
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R XCFxxP PROM as Configuration Master with CLK Input Pin as Clock Source X-Ref Target - Figure 16 CE OE/RESET CLK CLKOUT T CECC T OECC BUSY T OE (optional DATA CFCC T HCF CF ...
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R Symbol (7) Clock period (serial mode) when V (7) Clock period (serial mode) when V T CYCO (7) Clock period (parallel mode) when V (7) Clock period (parallel mode) when V (3) CLK Low time when ...
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R Symbol EN_EXT_SEL hold time from CF, CE, or OE/RESET when V T HXT EN_EXT_SEL hold time from CF, CE, or OE/RESET when V REV_SEL setup time to CF, CE, or OE/RESET when V T SRV REV_SEL setup time to ...
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R XCFxxP PROM as Configuration Master with Internal Oscillator as Clock Source X-Ref Target - Figure 17 CE OE/RESET CLKOUT T CEC T OEC BUSY T OE (optional DATA CFC T HCF CF EN_EXT_SEL T ...
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R Symbol BUSY setup time to CLKOUT when BUSY setup time to CLKOUT when V BUSY hold time to CLKOUT when BUSY hold time to CLKOUT when V ( CLKOUT delay when ...
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R AC Characteristics Over Operating Conditions When Cascading X-Ref Target - Figure 18 OE/RESET CE CLK CLKOUT (optional) DATA CEO Symbol Description CLK to output float delay when V = 2.5V or 3.3V T CCO CDF CLK to output float ...
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R Pinouts and Pin Descriptions The XCFxxS Platform Flash PROM is available in the VO20 and VOG20 packages. The XCFxxP Platform Flash PROM is available in the VO48, VOG48, FS48, and FSG48 packages. For package drawings, specifications, and additional information, ...
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R Table 13: XCFxxS Pin Names and Descriptions (Cont’d) Boundary Boundary-Scan Pin Name Scan Order Function TDO – Data Out VCCINT – VCCO – VCCJ – GND – DNC – XCFxxS VO20/VOG20 Pinout Diagram X-Ref Target - Figure 19 D0 ...
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R XCFxxP Pinouts and Pin Descriptions XCFxxP VO48/VOG48 and FS48/FSG48 Pin Names and Descriptions Table 14 provides a list of the pin names and descriptions for the XCFxxP 48-pin VO48/VOG48 and 48-pin FS48/FSG48 packages. Table 14: XCFxxP Pin Names and ...
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R Table 14: XCFxxP Pin Names and Descriptions (VO48/VOG48 and FS48/FSG48) (Cont’d) Boundary- Boundary- Pin Name Scan Scan Order Function 06 Data Out CEO 05 Output Enable EN_EXT_SEL 31 Data In REV_SEL0 30 Data In REV_SEL1 29 Data In BUSY ...
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R Table 14: XCFxxP Pin Names and Descriptions (VO48/VOG48 and FS48/FSG48) (Cont’d) Boundary- Boundary- Pin Name Scan Scan Order Function VCCINT – VCCO – VCCJ – GND – DNC – XCFxxP VO48/VOG48 Pinout Diagram X-Ref Target - Figure 20 DNC ...
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R XCFxxP FS48/FSG48 Pin Names Table 15: XCFxxP Pin Names (FS48/FSG48) Pin Pin Pin Name Number Number A1 GND E1 A2 GND E2 A3 OE/RESET E3 A4 DNC VCCINT F1 B2 VCCO ...
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R Ordering Information Device Number XCF01S XCF02S XCF04S Package Type VO20 = 20-pin TSSOP Package VOG20 = 20-pin TSSOP Package, Pb-free Device Number XCF08P XCF16P XCF32P Package Type VO48 = 48-pin TSOP Package VOG48 = 48-pin TSOP Package, Pb-free FS48 ...
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R Figure 22 through Figure 24 illustrate the part markings for each available package. Note: Package types can differ from the samples shown. X-Ref Target - Figure 22 Device Number Xilinx Logo X-Ref Target - Figure 23 TSOP Pin 1 ...
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R Revision History The following table shows the revision history for this document. Date Version 04/29/03 1.0 Xilinx Initial Release. 06/03/03 1.1 Made edits to all pages. 11/05/03 2.0 Major revision. 11/18/03 2.1 Pinout corrections as follows: • • • ...
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R • Added Pb-free package options VOG20, FSG48, and VOG48. 07/20/04 2.4 • • Section • • 10/18/04 2.5 • • • Table • Table • Table • Table • Added Virtex-4 LX/FX/SX configuration data to 03/14/05 2.6 • Corrected ...
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R • Notes for 12/29/05 2.8 (Cont’d) • Enhanced description under section • Enhanced description on design revision sampling under section • Figure 4 and Figure 5 renamed to • Value for • Block diagram in • Added Virtex-5 LX ...