m87c257-15xf7x STMicroelectronics, m87c257-15xf7x Datasheet - Page 7

• Manufacturer Part Number: m87c257-15xf7x
• Description: Address Latched 256k 32k X 8 Uv Eprom And Otp Eprom
• Manufacturer: STMicroelectronics

M87C257
2
2.1
2.2
2.3
Device operation
The modes of operation of the M87C257 are listed in the Operating Modes. A single power
supply is required in the read mode. All inputs are TTL levels except for V
for Electronic Signature.
Read mode
The M87C257 has two control functions, both of which must be logically active in order to
obtain data at the outputs. Chip Enable (E) is the power control and should be used for
device selection. Output Enable (G) is the output control and should be used to gate data to
the output pins, independent of device selection. Assuming that the addresses are stable
(AS = V
E to output (t
of G, assuming that E has been low and the addresses have been stable for at least t
t
systems. The processor multiplexed bus (AD0-AD7) may be tied to the M87C257's address
and data pins. No separate address latch is needed because the M87C257 latches all
address inputs when AS is low.
Standby mode
The M87C257 has a standby mode which reduces the active current from 30mA to 100µA
(Address Stable). The M87C257 is placed in the standby mode by applying a CMOS high
signal to the E input. When in the standby mode, the outputs are in a high impedance state,
independent of the G input.
Two Line Output Control
Because EPROMs are usually used in larger memory arrays, this product features a 2 line
control function which accommodates the use of multiple memory connection. The two line
control function allows:
For the most efficient use of these two control lines, E should be decoded and used as the
primary device selecting function, while G should be made a common connection to all
devices in the array and connected to the READ line from the system control bus. This
ensures that all deselected memory devices are in their low power standby mode and that
the output pins are only active when data is desired from a particular memory device.
GLQV
the lowest possible memory power dissipation,
complete assurance that output bus contention will not occur.
.The M87C257 reduces the hardware interface in multiplexed address-data bus
IH
) or latched (AS = V
ELQV
). Data is available at the output after delay of t
IL
), the address access time (t
AVQV
) is equal to the delay from
GLQV
from the falling edge
PP
Device operation
and 12V on A9
AVQV
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