74VCX32374GX Fairchild Semiconductor, 74VCX32374GX Datasheet

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74VCX32374GX

Manufacturer Part Number
74VCX32374GX
Description
IC FLIP FLOP 32BIT D 3ST 96FBGA
Manufacturer
Fairchild Semiconductor
Series
74VCXr
Type
D-Type Busr
Datasheet

Specifications of 74VCX32374GX

Function
Standard
Output Type
Tri-State Non Inverted
Number Of Elements
4
Number Of Bits Per Element
8
Frequency - Clock
250MHz
Delay Time - Propagation
1.5ns
Trigger Type
Positive Edge
Current - Output High, Low
24mA, 24mA
Voltage - Supply
1.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
96-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74VCX32374GX
Manufacturer:
Fairchild Semiconductor
Quantity:
10 000
© 2002 Fairchild Semiconductor Corporation
74VCX32374G
(Note 2)(Note 3)
74VCX32374
Low Voltage 32-Bit D-Type Flip-Flops
with 3.6V Tolerant Inputs and Outputs
General Description
The VCX32374 contains thirty-two non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP) and output enable (OE) are common to
each byte and can be shorted together for full 32-bit opera-
tion.
The 74VCX32374 is designed for low voltage (1.2V to
3.6V) V
The 74VCX32374 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Ordering Code:
Note 2: Ordering code “G” indicates Trays.
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Order Number
CC
applications with I/O compatibility up to 3.6V.
Package Number
BGA96A
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
DS500402
Features
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
value of the resistor is determined by the current-sourcing capability of the
driver.
1.2V to 3.6V V
3.6V tolerant inputs and outputs
t
Power-off high impedance inputs and outputs
Supports live insertion and withdrawal (Note 1)
Static Drive (I
Uses patented noise/EMI reduction circuitry
Latch-up performance exceeds 300 mA
ESD performance:
Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
PD
3.0 ns max for 3.0V to 3.6V V
Human body model
Machine model
24 mA @ 3.0V V
Package Descriptions
OH
CC
/I
OL
supply operation
)
200V
CC
CC
2000V
through a pull-up resistor; the minimum
December 2000
Revised November 2002
CC
www.fairchildsemi.com

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74VCX32374GX Summary of contents

Page 1

... Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide (Note 2)(Note 3) Note 2: Ordering code “G” indicates Trays. Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol © 2002 Fairchild Semiconductor Corporation Features 1.2V to 3.6V V supply operation CC 3 ...

Page 2

Connection Diagram (Top Thru View) Truth Tables Inputs – Inputs – ...

Page 3

Functional Description The 74VCX32374 consists of thirty-two edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte func- tioning identically, but independent of the other. The control pins can be shorted together ...

Page 4

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATED Outputs Active (Note 5) 0. Input Diode Current ( Output ...

Page 5

DC Electrical Characteristics Symbol Parameter V LOW Level Output Voltage OL I Input Leakage Current I I 3-STATE Output Leakage OZ I Power-OFF Leakage Current OFF I Quiescent Supply Current CC I Increase in I per Input CC CC Note ...

Page 6

AC Electrical Characteristics Symbol Parameter t Hold Time Pulse Width Note 8: For add approximately 300 ps to the AC maximum specification Dynamic Switching Characteristics Symbol Parameter V ...

Page 7

AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low ...

Page 8

AC Loading and Waveforms (V TEST PLH PZL PZH FIGURE 8. Waveform for Inverting and Non-Inverting Functions FIGURE 9. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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