cy14b101l Cypress Semiconductor Corporation., cy14b101l Datasheet
cy14b101l
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cy14b101l Summary of contents
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... Document #: 001-06400 Rev. *D PRELIMINARY 1-Mbit (128K x 8) nvSRAM Functional Description The Cypress CY14B101L is a fast static RAM with a nonvol- atile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while independent, nonvolatile data resides in the highly reliable QuantumTrap cell ...
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... Top View (Not To Scale CY14B101L HSB ...
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... WE goes low. AutoStore™ Operation The CY14B101L stores data to nvSRAM using one of three storage operations. These three operations are Hardware Store, activated by HSB, Software Store, activated by an address sequence, and AutoStore, on device power-down. ...
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... SRAM WRITE cycles requested after HSB goes low will be inhibited until HSB returns high. During any STORE operation, regardless of how it was initiated, the CY14B101L will continue to drive the HSB pin low, releasing it only when the STORE is complete. Upon completion of the STORE operation the CY14B101L will remain disabled until the HSB pin returns high ...
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... The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a non-volatile cycle. 2. While there are 17 address lines on the CY14B101L, only the lower 16 lines are used to control software modes. 3. I/O state depends on the state of OE. The I/O table shown assumes OE Low. ...
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... RECALL, or after a STORE, the WRITE will be inhibited until a negative transition detected. This protects against inadvertent writes during power-up or brown-out conditions. Noise Considerations The CY14B101L is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1 µF connected between V and V , using leads and traces that ...
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... V < > – pin and Rated CAP SS Test Conditions T = 25° MHz 3 CY14B101L = 25°C) ................................................... 1.0W [4] .................................... 15 mA Ambient Temperature V CC 0°C to +70°C 2.7V to 3.6V –40°C to +85°C 2.7V to 3.6V [5] Min. Max. Commercial Industrial ...
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... Input Pulse Levels.................................................. Input Rise and Fall Times (10% - 90%)........................ <5 ns Input and Output Timing Reference Levels....................1.5 V Document #: 001-06400 Rev. *D PRELIMINARY Test Conditions 3.0V OUTPUT 789Ω CY14B101L 32-SOIC 48-SSOP Unit °C/W TBD TBD °C/W TBD TBD R1 577Ω for tri-state specs R2 789Ω ...
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... Low when CE goes Low,the outputs remain in the High Impedance State Document #: 001-06400 Rev. *D PRELIMINARY 25 ns part Description Min. Max CY14B101L 35 ns part 45 ns part Min. Max. Min. Max. Unit ...
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... DATA VALID SWITCH. CY14B101L CY14B101L Min. Max. Unit 20 ms 12.5 ms 2.65 V μs 150 35 ns part 45 ns part Min. Max. Min. Max. Unit μ μ CY14B101L Min Max Unit μ [8,9,21] Page [+] Feedback ...
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... Note: 22 must be > V during address transitions. IH Document #: 001-06400 Rev. *D PRELIMINARY ACE t LZCE t DOE t LZOE t ACTIVE SCE PWE t SD DATA VALID t HZWE HIGH IMPEDANCE [21,22] CY14B101L HZCE t HZOE DATA VALID [8,21 LZWE Page [+] Feedback ...
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... SCE PWE t SD DATA VALID HIGH IMPEDANCE Figure 6. SRAM Write Cycle #2: CE Controlled t STORE t HRECALL Figure 7. AutoStore/Power-Up RECALL CY14B101L STORE occurs only No STORE occurs if a SRAM write without atleast one SRAM write has happened t STORE Page [+] Feedback ...
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... ADDRESS SCE OE t GLAX DQ (DATA) DATA VALID Figure 9. OE-controlled Software STORE/RECALL Cycle Document #: 001-06400 Rev. *D PRELIMINARY t RC ADDRESS # 6 DATA VALID t RC ADDRESS # 6 t STORE DATA VALID CY14B101L STORE RECALL HIGH IMPEDANCE [16 RECALL HIGH IMPEDANCE [16] Page [+] Feedback ...
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... DATA VALID DQ (DATA OUT) Soft Sequence Command ADDRESS ADDRESS # Document #: 001-06400 Rev. *D PRELIMINARY t STORE t HLBL t DELAY Figure 10. Hardware STORE Cycle 34 Soft Sequence Command t SS ADDRESS # 6 ADDRESS # 1 Figure 11. Soft Sequence Processing CY14B101L HIGH IMPEDANCE DATA VALID ADDRESS # 6 [18, 19] Page [+] Feedback ...
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... AutoStore + Software Store + Hardware Store Cypress Document #: 001-06400 Rev. *D PRELIMINARY Option Tape & Reel Blank - Std. Temperature Commercial (0 to 70° Industrial (–40 to 85°C) Package SOIC SSOP Data Bus Voltage 3.0V CY14B101L Speed Density: 101 - 1 Mb Page [+] Feedback ...
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... CY14B101L-SP25XCT 35 CY14B101L-SZ35XCT CY14B101L-SP35XCT 45 CY14B101L-SZ45XCT CY14B101L-SP45XCT 45 CY14B101L-SZ45XIT CY14B101L-SP45XIT CY14B101L-SZ45XI CY14B101L-SP45XI All of the above mentioned parts are of “Lead-Free” type. Shaded areas contain Advance information. Please contact your local Cypress sales representative for availability of these parts. Document #: 001-06400 Rev. *D PRELIMINARY Package Diagram Package Type ...
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... SEATING PLANE 0.090[2.286] 0.100[2.540] 0.004[0.101] 0.026[0.660] 0.032[0.812] 0.004[0.101] 0.0100[0.254] CY14B101L MIN. MAX. PART # S32.3 STANDARD PKG. SZ32.3 LEAD FREE PKG. 0.006[0.152] 0.021[0.533] 0.012[0.304] 0.041[1.041] 51-85127-*A Page ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY 48-pin Shrunk Small Outline Package (51-85061) CY14B101L 51-85061-*C Page [+] Feedback ...
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... Document History Page Document Title: CY14B101L 1-Mbit (128K x 8) nvSRAM Document Number: 001-06400 Issue REV. ECN NO. Date ** 425138 See ECN *A 437321 See ECN *B 471966 See ECN *C 503272 See ECN *D 597002 See ECN Document #: 001-06400 Rev. *D PRELIMINARY Orig. of Change Description of Change TUP ...