m58lw064a STMicroelectronics, m58lw064a Datasheet - Page 16

• Manufacturer Part Number: m58lw064a
• Description: 64 Mbit X16 And X16/x32, Block Erase Low Voltage Flash Memories
• Manufacturer: STMicroelectronics

M58LW064A, M58LW064B
Table 10. Burst Configuration Register
Note: 1. The BCR defines both the read mode and the burst configuration.
16/53
BCR mode bit
M14-M11
2. Synchronous burst length is defined as Word or Double-Word, the data bus width depends only on the WORD input.
3. A burst length of 8 is not available for x32 organisation.
4. At F
5. Latency 7 valid only for continuous burst. Otherwisw Latency = 8.
6. Latency 10 valid only for continuous burst. Otherwisw Latency = 12.
7. Latency 11 valid only for continuous burst. Otherwisw Latency = 12.
8. Latency 14 valid only for continuous burst. Otherwisw Latency = 16.
M2-M0
M15
M9
M8
M7
M6
M3
Asynchronous Page read is two Words or one Double-Word.
At F
K
K
> 50MHz when X-Latency = 10 or 12, Y-Latency = 2 independent of the value of M9.
= 66MHz when X-Lantency = 14 or 16, Y-Latency = 2 indepedent of the value of M9.
Read Select
Y-Latency
Valid Data Ready
Burst Type
Valid Clock Edge
Asynchronous
Burst Length
X-Latency
Description
(4)
(4)
(2)
0
1
0001
0010
0011
0100
0101
0110
1001
1010
1011
1101
0
1
0
1
0
1
0
1
0
1
100
101
001
010
111
Value
(1)
Synchronous Burst Read
Asynchronous Read
Reserved
7, only for F
8, only for F
9, only for F
10, only for F
11, only for F
12, only for F
13, only for F
14, only for F
16, only for F
One Burst Clock cycle
Two Burst Clock cycles
R valid Low during valid Burst Clock edge
R valid Low one data cycle before valid Burst Clock edge
Interleaved
Sequential
Falling Burst Clock edge
Rising Burst Clock edge
Random Read
Latch Enable Controlled Read
1 Word or Double-Word
2 Words or Double-Words
4 Words or Double-Words
8 Words or Double-Words
Continuous
K
K
K
K
K
K
K
K
K
= 33MHz
= 33MHz
= 33MHz
= 50MHz
= 50MHz
= 50MHz
= 50MHz
= 66MHz
= 66MHz
(5)
(6)
(7)
(8)
Description
(3)