br93lc56fv ROHM Co. Ltd., br93lc56fv Datasheet - Page 7

• Manufacturer Part Number: br93lc56fv
• Description: 2,048-bit Serial Electrically Erasable Prom
• Manufacturer: ROHM Co. Ltd.

(4) Reading (Figure 2)
When the read command is acknowledged, the data
(16 bits) for the input address is output serially. The
data is synchronized with the SK rise during A0 acqui-
sition and a “0” (dummy bit) is output. All further data is
output in synchronization with the SK pulse rises.
(5) Write enable (Figure 3)
These ICs are set to the write disabled state by the in-
ternal reset circuit when the power is turned on.
Therefore, before performing a write command, the
write enable command must be executed. When this
command is executed, it remains valid until a write
disable command is issued or the power supply is cut
Memory ICs
1 If the first data input following the rise of the start bit CS is "1", the start bit is acknowledged. Also, if a "1" is input following several zeroes in
2 Address auto increment function: These ICs are equipped with an address auto increment function which is effective only during reading operations.
succession, the "1" is recognized as the start bit, and subsequent operation commences. This applies also to all commands described subsequently.
With this function, if the SK clock is input following execution of one of the above reading commands, data is read from upper addresses in succession.
CS is held in HIGH state during automatic incrementing.
CS
SK
DI
DO
High-Z
1
1
1
2
1
0
DO
CS
SK
DI
4
0
A6
BR93LC56 / BR93LC56F / BR93LC56RF / BR93LC56FV
High-Z
A5
Fig. 2 Read cycle timing (READ)
1
A1
0
Fig. 3 Write enable cycle timing
11
0
A0
0
D15
12
1
D14
1
off. However, read commands can be used in either
the write enable or write disable state.
(6) Write (Figure 4)
This command writes the input 16-bit data (D15 to D0)
to the specified address (A6 to A0). Actual writing of
the data begins after CS falls (following the 27th clock
pulse after the start bit input), and the SK clock which
reads D0 falls.
If STATUS is not detected (CS is fixed at LOW), or if
STATUS is detected (CS = HIGH) at a maximum of 10
ms, in accordance with the time t
are accepted while DO is LOW (BUSY). Therefore, no
commands should be input during this period.
D1
27
D0
28
D15
2
D14
E / W
, no commands
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