at49ll080 ATMEL Corporation, at49ll080 Datasheet - Page 2

• Manufacturer Part Number: at49ll080
• Description: At49ll080 8-megabit Low-pin Count Flash Memory
• Manufacturer: ATMEL Corporation

Low Pin Count Interface
Address/Address
Multiplexed Interface
Block Diagram
2
AT49LL080
An internal Command User Interface (CUI) serves as the control center between the two
device interfaces (LPC and A/A Mux) and internal operation of the nonvolatile memory.
A valid command sequence written to the CUI initiates device automation.
Specifically designed for 3V systems, the AT49LL080 supports read operations at 3.3V
and sector erase and program operations at 3.3V and 12V V
ders the fastest program performance which will increase factory throughput, but is not
recommended for standard in-system LPC operation in the platform. Internal V
tion circuitry automatically configures the device for sector erase and program
operations. Note that, while current for 12V programming will be drawn from V
programming board solutions should design such that V
as V
The Low Pin Count (LPC) interface is designed to work with the I/O Controller Hub (ICH)
during platform operation.
The LPC interface consists primarily of a five-signal communication interface used to
control the operation of the device in a system environment. The buffers for this inter-
face are PCI compliant. To ensure the effective delivery of security and manageability
features, the LPC interface is the only way to get access to the full feature set of the
device. The LPC interface is equipped to operate at 33 MHz, synchronous with the PCI
bus.
The A/A Mux interface is designed as a programming interface for OEMs to use during
motherboard manufacturing or component pre-programming.
The A/A Mux refers to the multiplexed row and column addresses in this interface. This
approach is required so that the device can be tested and programmed quickly with
automated test equipment (ATE) and PROM programmers in the OEM’s manufacturing
flow. This interface also allows the device to have an efficient programming interface
with potentially large future densities, while still fitting into a 32-pin package. Only basic
reads, programming, and erase of the nonvolatile memory sectors can be performed
through the A/A Mux interface. In this mode LPC features, security features and regis-
ters are unavailable. A row/column (R/C) pin determines which set of addresses “rows
or columns” are latched.
CC
, and should assume that full programming current may be drawn from either pin.
I/O7 - I/O0
LAD (3:0)
GPI (4:0)
LFRAME
A10 - A0
ID (3:1)
RY/BY
CLK
TBL
INIT
R/C
WP
WE
OE
CE
INTERFACE
INTERFACE
A/A MUX
LPC
PP
RST
CONTROL
ARRAY
LOGIC
FLASH
draws from the same supply
PP
IC
. The 12V V
3273C–FLASH–5/03
PP
option ren-
PP
PP
detec-
, 3.3V