dm96s02 Fairchild Semiconductor, dm96s02 Datasheet - Page 3

• Manufacturer Part Number: dm96s02
• Description: Dual Retriggerable Resettable Monostable Multivibrator
• Manufacturer: Fairchild Semiconductor

Operation Notes
TIMING
1. An external resistor (R
2. The value of C
3. Polarized capacitors may be used directly. The ( ) ter-
4. The output pulse width t
5. The output pulse width for R
6. To obtain variable pulse width by remote trimming, the
are required as shown in the Logic Diagram. The value
of R
value available. If however, the capacitor has signifi-
cant leakage relative to V
may not represent the pulse width obtained.
minal of a polarized capacitor is connected to pin 1(15),
the ( ) terminal to pin 2(14) and R
remain positive with respect to pin 2(14) during the tim-
ing cycle. However, during quiescent (non-triggered)
conditions, pin 1(15) may go negative with respect to
pin 2(14) depending on values of R
ues of R
reverse polarity, pin 1(15) negative with respect to pin
2(14) is 500 mV. Most tantalum electrolytic capacitors
are rated for safe reverse bias operation up to 5% of
their working forward voltage rating; therefore, capaci-
tors having a rating of 10 WVdc or higher should be
used with the DM96S02 when R
1000 pF is determined as follows:
t
Where R
CX is in F, t is in ms.
should be determined from pulse width versus C
R
following circuit is recommended:
W
X
graphs.
X
0.55 R
may vary from 1.0 k
X
X
is in k , C
X
C
10 k
X
X
may vary from 0 to any necessary
the maximum amount of capacitor
X
X
is in pF, t is in ns or RT
) and an external capacitor (C
W
CC
to 2.0 M (DM96S02).
for R
X
/R
X
10 k
X
X
the timing equations
X
10 k .
10 k
X
and V
or C
. Pin 1(15) will
X
CC
and C
X
. for val-
1000 pF
is in k ,
X
X
X
or
)
3
7. Under any operating condition, C
8. V
TRIGGERING
1. The minimum negative pulse width into I0 is 8.0 ns; the
2. Input signals to the DM96S02 exhibiting slow or noisy
3. When non-retriggerable operation is required, i.e.,
4. An overriding active LOW level direct clear is provided
be kept as close to the circuit as possible to minimize
stray capacitance and reduce noise pickup.
frequency standards so that switching transients on
V
between one shots. Use of a 0.01 F to 0.1 F bypass
capacitor between V
circuit is recommended.
minimum positive pulse width into I1 is 12 ns.
transitions should use the positive trigger input I1 which
contains a Schmitt trigger.
when input triggers are to be ignored during quasi-sta-
ble state, input latching is used to inhibit retriggering.
on each multivibrator. By applying a LOW to the clear,
any timing cycle can be terminated or any new cycle
inhibited until the LOW reset input is removed. Trigger
inputs will not produce spikes in the output when the
reset is held LOW. A LOW-to-HIGH transition on C
will not trigger the DM96S02. If the C
coincident with a trigger transition, the circuit will
respond to the trigger.
CC
CC
and ground wiring should conform to good high
and ground leads do not cause interaction
CC
and ground located near the
X
and R
D
www.fairchildsemi.com
input goes HIGH
X
(Min) must
D