nlsf3t125 ON Semiconductor, nlsf3t125 Datasheet

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nlsf3t125

Manufacturer Part Number
nlsf3t125
Description
Quad Bus Buffer
Manufacturer
ON Semiconductor
Datasheet

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Part Number:
nlsf3t125MNR2
Manufacturer:
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Quantity:
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Part Number:
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NLSF3T125
Quad Bus Buffer
with 3−State Control Inputs
with silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS
low power dissipation.
High to place the output into the high impedance state.
used as a level converter for interfacing 3.3 V to 5.0 V, because it has
full 5.0 V CMOS level output swings.
between 0 V and 5.5 V are applied, regardless of the supply voltage.
The output structures also provide protection when V
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
Features
*For additional information on our Pb−Free strategy and soldering details, please
© Semiconductor Components Industries, LLC, 2006
May, 2006 − Rev. 4
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
The NLSF3T125 is a high speed CMOS quad bus buffer fabricated
The NLSF3T125 requires the 3−state control input (OE) to be set
The T125 inputs are compatible with TTL levels. This device can be
The NLSF3T125 input structures provide protection when voltages
The internal circuit is composed of three stages, including a buffer
High Speed: t
Low Power Dissipation: I
TTL−Compatible Inputs: V
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2.0 V to 5.5 V Operating Range
Low Noise: V
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: Human Body Model; > 2000 V,
Chip Complexity: 72 FETs or 18 Equivalent Gates
Pb−Free Package is Available*
A
H
L
X
Inputs
PD
OLP
= 3.8 ns (Typ) at V
= 0.8 V (Max)
OE
L
L
H
Machine Model; > 200 V
FUNCTION TABLE
CC
NLSF3T125
IL
= 4.0 mA (Max) at T
= 0.8 V; V
CC
= 5.0 V
IH
= 2.0 V
Output
A
Y
H
L
Z
CC
= 25°C
= 0 V. These
1
†For information on tape and reel specifications,
NLSF3T125MNR2
NLSF3T125MNR2G
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
(Note: Microdot may be in either location)
Device
.
ORDERING INFORMATION
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
MARKING DIAGRAM
Ç Ç Ç
Ç Ç Ç
http://onsemi.com
1
CASE 485G
16
QFN−16
(Pb−Free)
Package
QFN−16 3000/Tape & Reel
QFN−16
1
ALYW G
NLSF
T125
Publication Order Number:
G
3000/Tape & Reel
NLSF3T125/D
Shipping†

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nlsf3t125 Summary of contents

Page 1

... NLSF3T125 Quad Bus Buffer with 3−State Control Inputs The NLSF3T125 is a high speed CMOS quad bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The NLSF3T125 requires the 3−state control input (OE set High to place the output into the high impedance state ...

Page 2

... Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NLSF3T125 Active−Low Output Enables ...

Page 3

... Current Î Î Î Î Î Î Î Î Î Î Î Î NLSF3T125 Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 4

... Characteristic Quiet Output Maximum Dynamic V OL Quiet Output Minimum Dynamic V OL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage NLSF3T125 (Input 3.0 ns Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 5

... PHL PLH 1.5V Y Figure 3. TEST POINT OUTPUT DEVICE UNDER C * TEST L *Includes all probe and jig capacitance Figure 5. Test Circuit NLSF3T125 SWITCHING WAVEFORMS OE 1.5V 3.0V GND 1. 1.5V Y TEST POINT OUTPUT DEVICE UNDER TEST *Includes all probe and jig capacitance Figure 6. Test Circuit http://onsemi ...

Page 6

... CONDITION CAN NOT VIOLATE 0.2 MM max MINIMUM SPACING BETWEEN LEAD TIP AND FLAG MILLIMETERS DIM MIN MAX A 0.80 1.00 A1 0.00 0.05 A3 0.20 REF b 0.18 0.30 D 3.00 BSC D2 1.65 1.85 E 3.00 BSC E2 1.65 1.85 e 0.50 BSC K 0.18 TYP L 0.30 0.50 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NLSF3T125/D ...

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