dm74as651 Fairchild Semiconductor, dm74as651 Datasheet

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dm74as651

Manufacturer Part Number
dm74as651
Description
Octal Bus Transceiver And Register
Manufacturer
Fairchild Semiconductor
Datasheet
© 2003 Fairchild Semiconductor Corporation
DM74AS651WM
DM74AS651NT
DM74AS652WM
DM74AS652NT
DM74AS651 • DM74AS652
Octal Bus Transceiver and Register
General Description
These devices incorporate an octal transceiver and an
octal D-type register configured to enable transmission of
data from bus to bus or internal register to bus. The
DM74AS651 offers 64-Industrial grade product guarantee-
ing performance from 40 C to 85 C.
These bus transceivers feature totem-pole 3-STATE out-
puts designed specifically for driving highly-capacitive or
relatively low-impedance loads. The high-impedance state
and increased high-logic-level drive provide these devices
with the capability of being connected directly to and driv-
ing the bus lines in a bus-organized system without need
for interface or pull-up components. They are particularly
attractive for implementing buffer registers, I/O ports, bidi-
rectional bus drivers, and working registers.
The registers in the DM74AS651 and DM74AS652 are
edge-triggered D-type flip-flops. On the positive transition
of the clock (CAB or CBA), the input data is stored.
The SAB and SBA control pins are provided to select
whether real-time data or stored data is transferred. A LOW
input level selects real-time data and a HIGH level selects
stored data. The select controls have a “make before
break” configuration to eliminate a glitch which would nor-
mally occur in a typical multiplexer during the transition
between stored and real-time data.
The Enable (GAB and GBA) control pins provide four
modes of operation; real-time data transfer from bus A-to-
B, real-time data transfer from bus B-to-A, real-time bus A
and/or B data transfer to internal storage, or internal stored
data transfer to bus A and/or B.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number
Package Number
M24B
N24C
M24B
N24C
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
DS006325
Features
Switching specifications at 50 pF
Switching specifications guaranteed over full tempera-
ture and V
Advanced oxide-isolated, ion-implanted Schottky TTL
process
3-STATE buffer-type outputs drive bus lines directly
Guaranteed performance over industrial temperature
range ( 40 C to 85 C) in 64-grade products
Package Description
CC
range
October 1986
Revised July 2003
www.fairchildsemi.com

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dm74as651 Summary of contents

Page 1

... They are particularly attractive for implementing buffer registers, I/O ports, bidi- rectional bus drivers, and working registers. The registers in the DM74AS651 and DM74AS652 are edge-triggered D-type flip-flops. On the positive transition of the clock (CAB or CBA), the input data is stored. ...

Page 2

... LOW-to-HIGH transition on the clock inputs. Note 2: If the select control is LOW, the clocks can occur simultaneously. If the select control is HIGH, the clocks must be staggered in order to load both registers. www.fairchildsemi.com DATA I/O (Note 1) OPERATION OR FUNCTION A1 B1 DM74AS651 THRU THRU A8 B8 Isolation Input Input ...

Page 3

... Logic Diagrams DM74AS651 Schematics of Inputs and Outputs Equivalent of All Other Inputs DM74AS652 Typical of All DM74AS651, DM74AS652 Outputs 3 www.fairchildsemi.com ...

Page 4

... OH 4.5V, I Max OL 5. Control Inputs Ports I 5.5V, Control Inputs 2. Ports 5.5V, Control Inputs 0. Ports 5.5V, V 2.25V O 5.5V Outputs HIGH DM74AS651 Outputs LOW Outputs Disabled Outputs HIGH DM74AS652 Outputs LOW Outputs Disabled 4 Max Units 5 0 MHz ...

Page 5

... DM74AS651 Switching Characteristics Symbol Parameter f Maximum Clock Frequency V MAX t Propagation Delay Time R PLH LOW-to-HIGH Level Output C t Propagation Delay Time PHL HIGH-to-LOW Level Output t Propagation Delay Time PLH LOW-to-HIGH Level Output t Propagation Delay Time PHL HIGH-to-LOW Level Output ...

Page 6

DM74AS652 Switching Characteristics Symbol Parameter f Maximum Clock Frequency V MAX CC t Propagation Delay Time R PLH 1 LOW-to-HIGH Level Output Propagation Delay Time PHL HIGH-to-LOW Level Output t Propagation Delay Time PLH LOW-to-HIGH Level Output ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M24B 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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