ml6461 Micro Electronics Corporation, ml6461 Datasheet - Page 22

• Manufacturer Part Number: ml6461
• Description: Ntsc Video Encoder
• Manufacturer: Micro Electronics Corporation

ML6461
22
Note: B31 is MSB
DATA BIT
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
NAME
CC_284
CC_21
AC_DC
SUBCARRIER_OFF
CC_ALL
FIX_SCH
ACTIVE_ON
BURST ON
YDEL0
YDEL1
FRAME_MODE
FLD_FRM_MODE
SENSE_VSYNC
SWITCH_FIELD
SWITCH_UV
SEL_HSYNC0
SEL_HSYNC1
SENSE_HSYNC
OVERLAY_ON
FSYNC
WIDE_BLANK
JAPAN_BLANK
FULL_BAR
ANALOG_HRESET
ANALOG_HBLANK
HRESET_MODE
SLAVE_MODE
SELCCIR
SLAVE/MASTER
CBLANK
Reserved
Reserved
DESCRIPTION
Configures analog output buffers for AC or DC drive
Enables Closed Caption transmission on every line
Enable reset of subcarrier oscillator every other frame
to maintain SCH phase
Eliminate H & V intervals, suppress burst — for test only
Burst Available at all time — For test only
Delay/Advance luma channel
Delay/Advance luma channel
Configure FIELD pin as input or output
Switches even/odd fields
Switch Cr and Cb internally
Enables use of PHERR pin
Enable frame syncing
Enable transmission of Closed Caption data on line 284
Enable transmission of Closed Caption data on line 21
Select wide or narrow blanking
Removes 7.5 IRE setup in blanking and boosts Y & C gain
To handle 100% amplitude video (100% colorbars)
or digital blanking
Select CCIR656 rate or Square Pixel rate
Select slave or master mode
Composite Blanking
Set to 1 for Proper Operation
Set to1 for Proper Operation
Disable internal subcarrier oscillator - for test only
Configure FIELD pin to give odd/even or 1,2 and 3,4 info
Set vertical reset pulse polarity
Used to facilitate pixel synchronization
Used to facilitate pixel synchronization
Set horizontal reset pulse polarity
Selects position of horizontal reset
Select analog blanking with smooth transition at the edges
Select H reset at start of active video or start of H blanking
Select external H/V reset or embedded H/V reset
Table 6: Control Register (CNTR) Summary
<YDEL1, YDEL0> = 00 = Normal
<YDEL1, YDEL0> = 01= Delay luma 1 clock cycle
<YDEL1, YDEL0> = 10 = Advance luma 1 clock cycle,
<YDEL1, YDEL0> = 11= Advance luma 2 clock cycles
BIT CODE RANGE
0 = DC, 1 = AC
0 = Normal, 1= Disable oscillator
0 = Normal, 1 = Enable
0 = Not reset, 1 = Oscillator reset
0 = Normal, 1 = Test Mode
0 = Normal, 1 = Test Mode
0 = output, 1= input
0 = odd/even, 1= 1,2 or 3,4
0 = Falling edge, 1= Rising edge
0 = Normal, 1= switch even/odd
0 = Normal, 1= Switch Cr & Cb
See Figures 4, 5, 7, 8
See Figures 4, 5, 7, 8
0 = Falling edge, 1= Rising edge
0 = Disable, 1= Enable PHERR pin
0 = Disable, 1= Enable
0 = Disable, 1= Enable transmission
0 = Disable, 1= Enable transmission
0 = 9 lines of blanking, 1= 15 lines
0 = Normal, 1= Japanese NTSC
0 = Normal, 1 handles 100%Amp. Video
0 = Digital H blank edge,
1= Analog H blank edge
1= Analog blanking
1= Start of active
0=External H/V reset (H/V ext. source)
1=Embedded H/V reset (
0 = Square Pixel, 1= CCIR656
0 = Master mode, 1= Slave mode
0 = Disable, 1= Enable
0 = Digital blanking,
0 = Start of blanking,
SAV/EAV codes)