74actq74 Fairchild Semiconductor, 74actq74 Datasheet

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74actq74

Manufacturer Part Number
74actq74
Description
Quiet Series Dual D-type Positive Edge-triggered Flip-flop
Manufacturer
Fairchild Semiconductor
Datasheet
© 1999 Fairchild Semiconductor Corporation
74ACTQ74SC
74ACTQ74SJ
74ACTQ74PC
74ACTQ74
Quiet Series Dual D-Type
Positive Edge-Triggered Flip-Flop
General Description
The 74ACTQ74 is a dual D-type flip-flop with Asynchro-
nous Clear and Set inputs and complementary (Q, Q) out-
puts. Information at the input is transferred to the outputs
on the positive edge of the clock pulse. Clock triggering
occurs at a voltage level of the clock pulse and is not
directly related to the transition time of the positive-going
pulse. After the Clock Pulse input threshold voltage has
been passed, the Data input is locked out and information
present will not be transferred to the outputs until the next
rising edge of the Clock Pulse input.
The ACTQ74 utilizes Fairchild Quiet Series technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series
GTO
to a split ground bus for superior performance.
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering form.
Connection Diagram
FACT , FACT Quiet Series
Order Number
output control and undershoot corrector in addition
Package Number
and GTO
M14A
M14D
N14A
are trademarks of Fairchild Semiconductor Corporation.
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DS010920
features
Asynchronous Inputs:
Features
Pin Descriptions
D
CP
C
S
Q
D1
LOW input to S
LOW input to C
Clear and Set are independent of clock
Simultaneous LOW on C
I
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Guaranteed pin-to-pin skew AC performance
Improved latch-up immunity
4 kV minimum ESD immunity
TTL-compatible inputs
1
D1
1
CC
, D
, Q
1
both Q and Q HIGH
, S
, C
, CP
reduced by 50%
2
1
Package Description
D2
D2
, Q
Pin Names
2
2
, Q
2
D
D
(Set) sets Q to HIGH level
(Clear) sets Q to LOW level
D
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
and S
Data Inputs
March 1993
Revised November 1999
D
makes
Description
www.fairchildsemi.com

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74actq74 Summary of contents

Page 1

... Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop General Description The 74ACTQ74 is a dual D-type flip-flop with Asynchro- nous Clear and Set inputs and complementary (Q, Q) out- puts. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering ...

Page 2

Truth Table (Each Half) Inputs HIGH Voltage Level L ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Diode Current ( 0. 0. Input Voltage ( Output Diode Current ( ...

Page 4

AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay PLH PHL Propagation Delay PLH PHL n n ...

Page 5

FACT Noise Characteristics The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. Equipment: Hewlett Packard ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow www.fairchildsemi.com Package Number M14A 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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