ca3290 Intersil Corporation, ca3290 Datasheet - Page 4

• Manufacturer Part Number: ca3290
• Description: Bimos Dual Voltage Comparators With Mosfet Input, Bipolar Output
• Manufacturer: Intersil Corporation

Test Circuits and Waveforms
Circuit Description
The Basic Comparator
Figure 4 shows the basic circuit diagram for one of the two
comparators in the CA3290. It is generically similar to the
industry type “139” comparators, with PMOS transistors
replacing PNP transistors as input stage elements.
Transistors Q
stage, with Q
load and differential-to-single-ended converter. The
differential input at Q
in accordance with the input signal polarity. For example, if
+V
transistors Q
and Q
output is pulled positive when a load resistor is connected
between the output and V+.
In essence, Q
Q
providing gate oxide protection against input voltage
2
IN
and Q
INPUT
INPUT
1K
is greater than -V
1K
7
will be turned on, causing Q
1K
1K
3
, respectively, with zener diodes D
5
+
-
5
+15V
1
+
-
+15V
1
and Q
and Q
through Q
and Q
OUTPUT
OUTPUT
FIGURE 2. NON-INVERTING COMPARATOR RESPONSE TIME TEST CIRCUIT AND WAVEFORMS
5.1K
6
1
5.1K
6
FIGURE 3. INVERTING COMPARATOR RESPONSE TIME TEST CIRCUIT AND WAVEFORMS
4
and Q
will be turned off; Transistors Q
IN
serving as a mirror connected active
function as source followers to drive
, Q
OVERDRIVE
4
OVERDRIVE
comprise the differential input
GND
1
GND
4
, Q
INPUT
is amplified so as to toggle Q
4
INPUT
OVERDRIVE
2
, and current mirror
8
100mV
to be turned off. The
OVERDRIVE
1
OVERDRIVE
5mV
through D
20mV
CA3290, CA3290A
3
OVERDRIVE
, Q
20mV
4
4
,
6
5mV
OVERDRIVE
100mV
OVERDRIVE
transients (e.g., static electricity). The current flow in Q
Q
sources I
operated with a constant current load, their gate-to-source
voltage drops will be effectively constant as long as the input
voltages are within the common-mode range.
As a result, the input offset voltage (V
V
differential DC voltage is applied to the device for extended
periods of time at high temperatures.
Additional voltage gain following the first stage is provided
by transistors Q
offering the user a wide variety of options in applications. An
additional discrete transistor can be added if it becomes
necessary to boost the output sink current capability.
The detailed schematic diagram for one comparator and the
common current source biasing is shown on the front page.
PMOS transistors Q
BE(Q3)
4
is established at approximately 50
OVERDRIVE
OVERDRIVE
- V
GND
GND
1
and I
INPUT
GS(Q4)
INPUT
7
3
OVERDRIVE
OVERDRIVE
, respectively. Since Q
and Q
) will not be degraded when a large
9
100mV
through Q
5mV
8
. The collector of Q
20mV
OVERDRIVE
12
OVERDRIVE
are the current source
µ
20mV
GS(Q1)
A by constant current
1
and Q
5mV
OVERDRIVE
8
+ V
is open,
100mV
OVERDRIVE
4
BE(Q2)
are
1
and
-