isd5216 Winbond Electronics Corp America, isd5216 Datasheet - Page 16

• Manufacturer Part Number: isd5216
• Description: 8 To 16 Minutes Voice Record/playback Device With Integrated Codec
• Manufacturer: Winbond Electronics Corp America

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable
during the HIGH period of the clock pulse, as changes in the data line at this time will be interpreted
as a control signal. The same timing applies to both read and write.
The number of data bytes transferred between the start and stop conditions from transmitter to
receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is
a HIGH level signal put on the interface bus by the transmitter during which time the master generates
an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. In addition, a master receiver must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA line during the acknowledge clock pulse so
that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-
up and hold times must be taken into consideration). A master receiver must signal an end of data to
the transmitter by not generating an acknowledge on the last byte that has been clocked out of the
slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a
stop condition.
BY TRANSMITTER
DATA OUTPUT
DATA OUTPUT
BY RECEIVER
7.3.3. Bit transfer
7.3.4. ACKNOWLEDGE
SCL FROM
MASTER
SDA
SCL
condition
START
S
1
Acknowledge on the I
data valid
data line
stable;
Bit transfer on the I
- 16 -
2
changed
allowed
of data
2
C-bus
not acknowledge
2
acknowledge
C-Bus
acknowledgement
dock pulse for
9
ISD5216