isd4004 Winbond Electronics Corp America, isd4004 Datasheet
isd4004
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isd4004 Summary of contents
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... ISD4004 SERIES SINGLE-CHIP, MULTIPLE-MESSAGES VOICE RECORD/PLAYBACK DEVICES 8-, 10-, 12-, AND 16-MINUTE DURATION Publication Release Date: July 16, 2007 - 1 - Revision 1.3 ...
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... The CMOS-based devices include an on-chip oscillator, anti-aliasing filter, smoothing filter, AutoMute feature, audio amplifier, and high density multilevel Flash memory array. The ISD4004 series is designed to be used in a microprocessor- or microcontroller-based system. Address and control are accomplished through a Serial Peripheral Interface (SPI) or Microwire Serial Interface to minimize pin count ...
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... Power-down feature to reduce power consumption • Available in die, PDIP, SOIC, and TSOP • Packaged type: Lead-Free • Temperature: • Commercial (die): 0°C to +50°C - Commercial (packaged units): 0°C to +70°C - Industrial (packaged units): -40°C to +85°C - ISD4004 SERIES Publication Release Date: July 16, 2007 - 3 - Revision 1.3 ...
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... V V CCA SSA SSA SSA Timing Sampling Clock 5-Pole Active Analog Transceivers Antialiasing Filter 3,840K Cell Nonvolatile Multilevel Storage Array Device Control V V SCLK SS MOSI MISO INT SSD CCD - 4 - ISD4004 SERIES 5-Pole Active Smoothing Filter TM AutoMute Feature Amp AUDOUT RAC AM CAP ...
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... Plastic Dual Inline Package (PDIP) ............................................................... 31 12.3. 28-Lead 8x13.4mm Plastic Thin Small Outline Package (TSOP) Type 1 - IQC ...................... 32 12.4. 28-Lead 8x13.4mm Plastic Thin Small Outline Package (TSOP) Type 1 ................................ 33 12.5. Die Information ......................................................................................................................... 34 13. ORDERING INFORMATION........................................................................................................... 36 14. VERSION HISTORY ....................................................................................................................... 37 ISD4004 SERIES Publication Release Date: July 16, 2007 - 5 - Revision 1.3 ...
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... ISD4004 SOIC / PDIP ISD4004 TSOP - 6 - ISD4004 SERIES SCLK V CCD XCLK INT RAC V SSA CCA ANA IN+ ANA IN CCA ANA IN+ 25 ANA IN ...
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... Slave Select: This input, when LOW, will select the ISD4004 device. 10 Master Out Slave IN: This is the serial input to the ISD4004 device when it is configured as slave. The master microcontroller places data on the MOSI line one half-cycle before the rising edge of SCLK for clocking into the device. 11 Master In Slave Out: This is the serial output (open drain) of the ISD4004 device ...
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... In the differential-input mode, the maximum input signal at ANA IN+ should be 16 mVp-p capacitively coupled for optimal signal quality. The circuit connections for the two modes are shown in Figure ISD4004 SERIES FUNCTION .. CCA ...
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... INT Supply Voltage: To minimize noises, the analog and digital circuits in the ISD4004 devices use separate power busses. These +3V busses are brought out to separate pins and should be tied together as close to the supply as possible. In addition, these supplies should be decoupled as close to the package as possible. ...
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... The duty cycle on the input clock is not critical, as the clock is immediately divided by two. If the XCLK is not used, this input must be connected to ground. 8 Serial Clock: This is the input clock to the ISD4004 device generated by microcontoller) and is used to synchronize the data transfer in and out of the device through the MOSI and MISO lines, respectively ...
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... F Input Signal 16m Vp-p Input Signal 16m Vp-p 180 ° μ 0.1 F Differential Input Mode FIGURE 1: ISD4004 SERIES ANA IN MODES RAC FIGURE 2: RAC TIMING WAVEFORM DURING NORMAL OPERATION Internal to the device ANA IN+ 3K Ω 3K Ω ANA IN- Internal to the device ANA IN+ 3K Ω 3K Ω ...
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... In addition, the device can be re- recorded typically over 100,000 times. Memory Architecture The ISD4004 series contains a total of 3,840K Flash memory cells, which is organized as 2,400 rows of 1,600 cells each. The address bits (A0-A15) are used to access various rows for multiple messages of different durations. ...
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... SCLK signal, with LSB first. 4. Playback and record operations are initiated when the device is enabled by asserting the pin LOW, shifting in an opcode and an address data to the ISD4004 device (refer to the Opcode Summary in the following page). 5. The opcodes contain <16 address bits> and <8 control bits>. ...
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... Message Cueing can be selected only at the beginning of a playback operation the Interrupt data is shifted out of the ISD4004, control and address data are being shifted in. Care should be taken such that the data shifted in is compatible with current system operation possible to read interrupt data and start a new operation at the same time ...
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... Ignore Address Bit (IAB) Power Up (PU) Play/Record (P/R) RUN P10 P11 P12 P13 P14 P15 st bit shifted into the ISD4004. st bit shifted out from the ISD4004. FIGURE 4: SPI PORT - 15 - ISD4004 SERIES A15 Select Logic ...
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... IAB should be changed before the end of that row (see RAC timing). Otherwise the ISD4004 will repeat the operation from the same row address. For memory management, the Row Address Clock (RAC) signal and IAB can be used to move around the memory segments. ...
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... In this mode, the messages are skipped 1,600 times faster than the normal playback mode. Power-Up Sequence The ISD4004 will be ready for an operation after power-up command is sent and followed by the T timing (25 ms for 8 KHz sampling rate). Refer to the AC timing table for other T to different sampling rates. ...
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... TIMING DIAGRAMS SS SCLK M OSI (TRISTATE) M ISO SS SCLK LSB A8 MOSI LSB OVF EOM MISO T SSS T T DIH SCKlow T DIS T PD LSB FIGURE 5: TIMING DIAGRAM A9 A10 FIGURE 6: 8-BIT COMMAND FORMAT - 18 - ISD4004 SERIES T SSH T SSm in T SCKhi ...
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... Data ANA IN ANA OUT FIGURE 8: PLAYBACK/RECORD AND STOP CYCLE BYTE 2 A9 A10 A11 A12 A13 A14 A15 P10 P11 P12 P13 P14 P15 Publication Release Date: July 16, 2007 - 19 - ISD4004 SERIES BYTE Stop ...
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... Note: Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum ratings may affect device reliability and performance. Functional operation is not implied at these conditions. SS pins SS pins - 20 - ISD4004 SERIES VALUES 150°C -65°C to +150°C (V –0.3V +0.3V – ...
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... TABLE 8: OPERATING CONDITIONS (DIE) CONDITIONS Commercial operating temperature range [1] Supply voltage ( [2] Ground voltage ( [ CCA CCD [ SSA SSD ISD4004 SERIES 0°C to +70°C -40°C to +85°C +2.7V to +3.3V 0V 0°C to +50°C +2.7V to +3.3V 0V Publication Release Date: July 16, 2007 - 21 - VALUES VALUES Revision 1.3 ...
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... EXT R 2.2 3.0 ANA IN ANA IN ARP = 25°C and V = 3.0V and all other pins floating. SSA SSA - 22 - ISD4004 SERIES [1] [2] MAX UNITS [3] [ µA ±1 µ ...
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... Publication Release Date: July 16, 2007 - 23 - ISD4004 SERIES [2] UNITS CONDITIONS [5] KHz [5] KHz [5] KHz [5] KHz [3][7] KHz 3 dB Roll-Off Point [3][7] KHz 3 dB Roll-Off Point [3][7] KHz 3 dB Roll-Off Point [3][7] KHz 3 dB Roll-Off Point ...
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... For optimal signal quality, this maximum limit is recommended. [10] When a record command is sent, T [11] Measured with AutoMute feature disabled. = 3.0V and timing measurement at 50% of Vcc level. CC maximum for ANA IN+ and ANA IN the first row address. RAC RAC RACL - 24 - ISD4004 SERIES at 32 mVp-p. IN ...
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... OL V OL1 0 THD A 23 ARP = 3.0V. Sampling Frequency can vary as much as ±2.25 percent = 25°C and and all other pins floating. SSA SSA - 25 - ISD4004 SERIES [1] [2] MAX UNITS ...
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... SSmin T 400 SCKhi T 400 SCKlow 3.0V and timing measurement at 50% of Vcc level. CC Ω MISO Ω 50pF (Includes scope and fixture capacitance ISD4004 SERIES [1] MAX UNITS CONDITIONS nsec nsec nsec nsec 500 nsec 500 nsec µsec nsec nsec 1,000 KHz ...
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... C10 μ 0 ANA IN RAC 14 AM CAP 25 12 INT C5 13 μ XCLK PDIP / SOIC ISD4004 SERIES V CC μ μ μ μ 10K R4 R3 100 100K POT ...
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... ANA IN+ R1 10K 24 RAC 14 AM CAP C5 25 INT 1 F μ XCLK μ Ω 4.7 K Ω 4.7 K PDIP / SOIC - 28 - ISD4004 SERIES μ LINE OUT 100 100K POT -IN GAIN-OUT J4 3 V01 ...
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... ANA IN+ R1 10K 24 RAC 14 AM CAP C5 25 INT 1 F μ XCLK μ Ω 4.7 K Ω 4.7 K PDIP / SOIC - 29 - ISD4004 SERIES μ 100 100K POT -IN GAIN-OUT J4 3 V01 10 14 ...
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... Note: Lead coplanarity to be within 0.004 inches (SOIC) MALL UTLINE INCHES Nom Max Min 0.706 0.711 17.81 0.101 0.104 2.46 0.296 0.299 7.42 0.009 0.0115 0.127 0.016 0.019 0.35 0.050 0.406 0.410 10.16 0.032 0.040 0. ISD4004 SERIES MILLIMETERS Nom Max 17.93 18.06 2.56 2.64 7.52 7.59 0.22 0.29 0.41 0.48 1.27 10.31 10.41 0.81 1.02 ...
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... G 0.055 0.060 H 0.100 J 0.008 0.010 S 0.070 0.075 q 0° (PDIP) UAL NLINE ACKAGE MILLIMETERS Max Min 1.455 36.70 0.075 1.65 0.625 15.24 0.550 13.46 0.19 0.38 0.135 3.18 0.022 0.38 0.065 1.40 0.012 0.20 0.080 1.78 15° 0° Publication Release Date: July 16, 2007 - 31 - ISD4004 SERIES Nom Max 36.83 36.96 3.81 1.78 1.91 15.88 13.72 13.97 4.83 3.43 0.46 0.56 1.52 1.62 2.54 0.25 0.30 1.91 2.03 15° Revision 1.3 ...
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... A 0.040 0.95 2 0.035 0.041 b 0.17 0.007 0.008 0.011 c 0.10 0.004 0.008 0.006 D 11.70 0.465 0.469 0.461 E 0.311 0.315 0.319 7.90 H 0.520 0.528 0.536 13. 0.022 L 0.50 0.020 0.028 0.024 L 1 0.031 Y 0.000 0.004 0.00 θ ISD4004 SERIES (TSOP IQC YPE 1.20 0.15 1.00 1.05 0.20 0.27 0.15 0.21 11.80 11.90 8.10 8.00 13.60 13.40 0.55 0.70 0.60 0.80 0. ...
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... Nom Max Min 0.528 0.535 13.20 0.465 0.469 11.70 0.315 0.319 7.90 0.006 0.05 0.009 0.011 0.17 0.0217 0.039 0.041 0.95 3° 6° 0° 0.022 0.028 0.50 0.008 0. ISD4004 SERIES (TSOP YPE MILLIMETERS Nom Max 13.40 13.60 11.80 11.90 8.00 8.10 0.15 0.22 0.27 0.55 1.00 1.05 3° 6° 0.55 ...
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... NFORMATION ISD4004 Series Die Dimensions (with scribe line 166.6 ± 1 mils Y: 385.0 ± 1 mils [2] Die Thickness o 11.5 ± 0.5 mils Pad Opening o Single pad microns Double pad: 180 x 90 microns Notes: [1] The backside of die is internally connected to V damage may occur. ...
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... AutoMute ANA IN- Inverting Analog Input ANA IN+ Noninverting Analog Input [1] V Analog Power Supply CCA [1] V Analog Power Supply CCA Note: [1] Double bond recommended if treated as one pad. ISD4004 SERIES P C ERIES AD OORDINATIONS X Axis (µm) 1885.2 1483.8 794.8 564.8 387.9 169.5 -14.7 -198.1 -1063.7 -1325 ...
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... Order # Part # Order # ISD4004-10MX I4410X ISD4004-10MPY I4410PY ISD4004-10MSY I4410SY I4410SYI ISD4004-12MSI I4412SYI ISD4004-10MEY I4410EY I4410EYI ISD4004-12MEI I4412EYI - 36 - ISD4004 SERIES Special Temperature Field : Blank = Commercial Package (0° 70°C) or Commercial Die (0° 50° Industrial (-40° 85°C) Lead-Free Type Lead-Free 12 Minutes ...
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... Revise disclaim section. 1.2 Oct. 2005 Revise Packaging information. 1.3 Jul. 2007 Remove the leaded package option Remove the extended temperature option Update the external clock description Revise Ordering Information section DESCRIPTION RACLO RACL parameter. ARP Publication Release Date: July 16, 2007 - 37 - ISD4004 SERIES Revision 1.3 ...
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... ChipCorder datasheet supersedes all data for the ISD ChipCorder products All rights reserved. ChipCorder ® is the trademark of Silicon Storage Technology, Inc. All other trademarks - 38 - ISD4004 SERIES ® ® ChipCorder ® ® and ISD are trademarks of ...