sc1486aitstr Semtech Corporation, sc1486aitstr Datasheet - Page 17

• Manufacturer Part Number: sc1486aitstr
• Description: Complete Ddr1/2/3 Power Supply Controller
• Manufacturer: Semtech Corporation

Layout Guidelines
One (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and
maximize heat dissipation. The IC ground references, VSSA1 and VSSA2, should be kept separate from power
ground. All components that are referenced to them should connect to them locally at the chip. VSSA1 and VSSA2
should connect to power ground at their respective output capacitors only.
Feedback traces must be kept far away from noise sources such as switching nodes, inductors and gate drives.
Route feedback traces with their respective VSSAs as a differential pair from the output capacitor back to the chip.
Run them in a “quiet layer” if possible.
Chip decoupling capacitors (VDDP, VCCA) should be located next to the pins and connected directly to them on the
same side.
Power sections should connect directly to the ground plane(s) using multiple vias as required for current handling
(including the chip power ground connections). Power components should be placed to minimize loops and reduce
losses. Make all the connections on one side of the PCB using wide copper filled areas if possible. Do not use
“minimum” land patterns for power components. Minimize trace lengths between the gate drivers and the gates of
the MOSFETs to reduce parasitic impedances (and MOSFET switching losses), the low-side MOSFET is most critical.
Maintain a length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current handling
requirement (and to reduce parasitics) if routed on more than one layer
Current sense connections must always be made using Kelvin connections to ensure an accurate signal.
We will examine the SC1486A DDR2 reference design used in the Design Procedure section while explaining the
layout guidelines in more detail.
1.8V, 10A
Sample DDR2 Design Using SC1486A
PWR_SRC = 7.5V to 20.5V
VDDQ = 1.8V @ 10A
VTT = 0.9V @ 1.5A
Schematic is drawn to emphasize required grounding scheme
POWER MANAGEMENT
Application Information (Cont.)
2006 Semtech Corp.
C12
0u1
0402
10u/25V
1210
C4
+
10u/25V
C13
330u/25m
7343
R7
0R
0402
1210
C3
0u1/25V
PGOOD1
+
0603
C14
330u/25m
7343
C2
L1
R14 470k
2n2/50V
2u4
0402
0402
PWR_SRC
C1
5VSUS
R15 470k
8
7
6
5
8
7
6
5
IRF7811AV
FDS6676S
0402
D
D
D
D
D
D
D
D
Figure 4: DDR2 Reference Design and Layout Example
PGOOD2
S
S
S
G
S
S
S
G
Q2
Q3
1
2
3
4
1
2
3
4
1.8V
VSSA1
C10 0u1
C17
27p
0402
R5
0603
0402
13k3
45k3
0402
17k4
0402
R3
1M
0402
R10
R13
VCCA1
TON1
D1
SOD
323
C20
1n
0402
R1 10R
0402
C8
1u
0603
PGD1
VCCA1
VCCA1
C21
1u
0603
5VSUS
R2
27
22
24
26
23
25
28
3
1
6
7
5
4
2
10R
0402
U1
17
VDDP1
PGND1
DH1
BST1
LX1
ILIM1
DL1
PGD1
EN/PSV1
VOUT1
FB1
TON1
VCCA1
VSSA1
VCCA2
SC1486A
REFOUT
PGND2
VSSA2
VDDP2
VCCA2
REFIN
TON2
BST2
ILIM2
PGD2
FB2
DH2
DL2
LX2
17
15
20
21
19
18
16
13
12
8
10
9
11
14
PGD2
REFOUT
VCCA2
5VRUN
C9
1u
0603
C22
1u
0603
TON2
D2
SOD
323
C23
1n
0402
0.9V
VSSA2
R4
649k
0402
R11 10R
0402
R6
C11 0u1
4k32
FDS6982S
0402
C18
1u
0603
0603
Q1
4
3
8
2
C19
0u1
0402
5
R12
10k0
0402
6
1
R9
PWR_SRC
7
10k0
0402
SC1486A
1.8V
C7
2n2/50V
0402
L2
www.semtech.com
3u9
220u/25m
7343
0402
C15
C6
0u1/25V
0603
R8
0R
+
C5
10u/25V
1210
C16
0u1
0402
0.9V, 1.5A