w83977ag Winbond Electronics Corp America, w83977ag Datasheet - Page 68

• Manufacturer Part Number: w83977ag
• Description: W83977f With 3rd Uart For Ir, Pb-free
• Manufacturer: Winbond Electronics Corp America

7.4.1
These two registers are the same as legacy IR baud rate divisor latch in SET 1.Reg0~1. In advanced
SIR/ASK-IR mode, user should program these registers to set baud rate. This is to prevent backward
operation from occurring.
7.4.2
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Advanced IR
Reset Value
MODE
W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
DMATHL
Reg0, 1 - Advanced Baud Rate Divisor Latch (ABLL/ABHL)
Reg2 - Advanced IR Control Register 1 (ADCR1)
0
1
BR_OUT - Baud Rate Clock Output
When written to 1, the programmed baud rate clock will be output to DTR pin. This bit is
only used to test baud rate divisor.
Reserved, write 0.
EN_LOUT - Enable Loopback Output
A write to 1 will enable transmitter to output data to IRTX pin when loopback operation.
Internal data can be verified through an output pin by setting this bit.
ALOOP - All Mode Loopback
A write to 1 will enable loopback in all modes.
D_CHSW - DMA TX/RX Channel Swap
If only one DMA channel operates in MIR/FIR mode, then the DMA channel can be
swapped.
A write to 1 will enable output data when ALOOP=1.
DMATHL - DMA Threshold Level
Set DMA threshold level as shown in the following table.
BR_OUT
BIT 7
0
BIT 6
D_CHSW
0
-
0
1
16-BYTE
EN_LOUT
13
23
BIT 5
0
TX FIFO THRESHOLD
ALOOP
-60
BIT 4
DMA Channel Selected
0
Receiver (Default)
Transmitter
D_CHSW
BIT 3
32-BYTE
0
13
7
DMATHL
BIT 2
0
RX FIFO THRESHOLD
DMA_F
BIT 1
(16/32-BYTE)
0
10
4
ADV_SL
BIT 0
0