w83628f Winbond Electronics Corp America, w83628f Datasheet - Page 10

no-image

w83628f

Manufacturer Part Number
w83628f
Description
Pci To Isa Bridge Set
Manufacturer
Winbond Electronics Corp America
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
W83628F
Manufacturer:
Winbond
Quantity:
18
Part Number:
W83628F
Manufacturer:
WINBOND
Quantity:
1 000
7.1.3 ISA Interface Signals
SA[19:17]
SA[16:0]
SD[15:0]
AEN
IOR#
IOW#
IOCHRDY
SYSCLK
RSTDRV
IOCS16#
SBHE#
IOCHK#
SYMBOL
98-96
94-83
81-77
110-
8-15
107,
104,
103,
101,
100,
118
120
121
116
124
105
PIN
99
74
18
OUT 24t
OUT 24t
OUT 24t
OUT 24t
I/O 24t
I/O 24t
I/O 24t
I/O 24t
I/O 24t
I/O 24t
I/O
IN t
IN t
System Address Bus. These are the upper address lines that
define the ISA’s byte granular address space (up to 1 Mbyte).
SA[19:17] are at an unknown state upon PCIRST#.
System Address Bus. These are the bi-directional lower
address lines that define the ISA’s byte granular address space
(up to 1 Mbyte). SA[16:0] are at an unknown state upon
PCIRST#.
System Data. SD[15:0] provide the 16-bit data path for devices
residing on the ISA Bus. The W83628F tri-states SD[15:0] during
PCIRST#.
Address Enable. AEN is asserted during DMA cycles. This
signal is also driven high during W83628F initiated refresh
cycles. AEN is driven low upon PCIRST#.
I/O Read. IOR# is the command to an ISA I/O slave device that
the slave may drive data on to the ISA data bus (SD[15:0]).
I/O Write. IOW# is the command to an ISA I/O slave device that
the slave may latch data from the ISA data bus (SD[15:0]).
I/O Channel Ready. Resources on the ISA Bus negate
IOCHRDY to indicate that additional time (wait states) is required
to complete the cycle.
bus. The SYSCLK is generated by dividing PCICLK by 3 or 4.
Reset Drive. W83628F asserts RSTDRV to reset devices that
reside on the ISA Bus. The W83628F asserts this signal while
the PCIRST# is asserted.
16-bit I/O Chip Select. This signal is driven by I/O devices on
the ISA Bus to indicate that they support 16-bit I/O bus cycles.
System Byte High Enable. SBHE# asserted indicates that a
byte is being transferred on the upper byte (SD[15:8]) of the data
bus. SBHE# is at an unknown state upon PCIRST#.
the ISA bus during on detection of an error.
ISA System Clock. SYSCLK is the reference clock for the ISA
I/O Channel Check. IOCHK# can be driven by any resource on
-10-
W83628F & W83629D
FUNCTION

Related parts for w83628f