lm25119psqx National Semiconductor Corporation, lm25119psqx Datasheet - Page 14

• Manufacturer Part Number: lm25119psqx
• Description: Lm25119 Wide Input Range Dual Synchronous Buck Controller
• Manufacturer: National Semiconductor Corporation

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Hiccup Mode Current Limiting
To further protect the regulator during prolonged current limit
conditions, an internal counter counts the PWM clock cycles
during which cycle-by-cycle current limiting occurs. When the
counter detects 256 consecutive cycles of current limiting, the
regulator enters a low power dissipation hiccup mode with the
HO and LO outputs disabled. The restart timer pin, RES, and
an external capacitor configure the hiccup mode current lim-
iting. A capacitor on the RES pin (C
the controller will remain in low power standby mode before
automatically restarting. A 10µA current source charges the
RES pin capacitor to the 1.25V threshold which restarts the
overloaded channel. The two regulator channels operate in-
dependently. One channel may operate normally while the
other is in the hiccup mode overload protection. The hiccup
mode commences when either channel experiences 256 con-
secutive PWM cycles with cycle-by-cycle current limiting. If
that occurs, the overloaded channel will turn off and remain
off for the duration of the RES pin timer.
The hiccup mode current limiting function can be disabled.
The RES configuration is latched during initial power-up when
UVLO is above 1.25V and VCC1 and VCC2 are above their
UV thresholds, determining hiccup or non-hiccup current lim-
iting. If the RES pin is tied to VCC at initial power-on, hiccup
current limit is disabled.
Soft-Start
The soft-start feature allows the regulator to gradually reach
the steady state operating point, thus reducing start-up
stresses and surges. The LM25119 will regulate the FB pin to
the SS pin voltage or the internal 0.8V reference, whichever
is lower. At the beginning of the soft-start sequence when SS
= 0V, the internal 10µA soft-start current source gradually in-
creases the voltage on an external soft-start capacitor (C
connected to the SS pin resulting in a gradual rise of the FB
and output voltages.
Either regulator channel of the LM25119 can be disabled by
pulling the corresponding SS pin to AGND.
Diode Emulation
A fully synchronous buck regulator implemented with a free-
wheel MOSFET rather than a diode has the capability to sink
current from the output in certain conditions such as light load,
over-voltage or pre-bias startup. The LM25119 provides a
diode emulation feature that can be enabled to prevent re-
verse (drain to source) current flow in the low side free-wheel
MOSFET. When configured for diode emulation, the low side
MOSFET is disabled when reverse current flow is detected.
The benefit of this configuration is lower power loss at no load
or light load conditions and the ability to turn on into a pre-
biased output without discharging the output. The diode em-
ulation mode allows for start-up into pre-biased loads, since
it prevents reverse current flow as the soft-start capacitor
charges to the regulation level during startup. The negative
effect of diode emulation is degraded light load transient re-
sponse times. Enabling the diode emulation feature is rec-
ommended and allows discontinuous conduction operation.
The diode emulation feature is configured with the DEMB pin.
To enable diode emulation, connect the DEMB pin to ground
or leave the pin floating. If continuous conduction operation is
desired, the DEMB pin should be tied to either VCC1 or VCC2.
RES
) determines the time
SS
)
14
HO and LO Output Drivers
The LM25119 contains a high current, high-side driver and
associated high voltage level shift to drive the buck switch of
each regulator channel. This gate driver circuit works in con-
junction with an external diode and bootstrap capacitor. A
0.1µF or larger ceramic capacitor, connected with short traces
between the HB pin and SW pin, is recommended. During the
off-time of the high-side MOSFET, the SW pin voltage is ap-
proximately 0V and the bootstrap capacitor charges from
VCC through the external bootstrap diode. When operating
with a high PWM duty cycle, the buck switch will be forced off
each cycle for 320ns to ensure that the bootstrap capacitor is
recharged.
The LO and HO outputs are controlled with an adaptive dead-
time methodology which insures that both outputs are never
enabled at the same time. When the controller commands HO
to be enabled, the adaptive dead-time logic first disables LO
and waits for the LO voltage to drop. HO is then enabled after
a small delay. Similarly, the LO turn-on is disabled until the
HO voltage has discharged. This methodology insures ade-
quate dead-time for any size MOSFET.
Care should be exercised in selecting an output MOSFET
with the appropriate threshold voltage, especially if VCC is
supplied from the regulator output. During startup at low input
voltages the MOSFET threshold should be lower than the 4V
VCC under-voltage lockout threshold. Otherwise, there may
be insufficient VCC voltage to completely turn on the MOS-
FET as VCC under-voltage lockout is released during startup.
If the buck switch MOSFET gate drive is not sufficient, the
regulator may not start or it may hang up momentarily in a
high power dissipation state. This condition can be avoided
by selecting a MOSFET with a lower threshold voltage or if
VCC is supplied from an external source higher than the out-
put voltage. If the minimum input voltage programmed by the
UVLO pin resistor divider is above the VCC regulation level,
this precaution is of no concern.
Maximum Duty Cycle
When operating with a high PWM duty cycle, the buck switch
will be forced off each cycle for 320ns to ensure the boot-strap
capacitor is recharged and to allow time to sample and hold
the current in the low side MOSFET. This forced off-time limits
the maximum duty cycle of the controller. When designing a
regulator with high switching frequency and high duty cycle
requirements, a check should be made of the required maxi-
mum duty cycle (including losses) against the graph shown
in
The actual maximum duty cycle will vary with the operating
frequency as follows:
Figure
5.
(6)