lm2507gr National Semiconductor Corporation, lm2507gr Datasheet - Page 2

• Manufacturer Part Number: lm2507gr
• Description: Low Power Mobile Pixel Link Mpl Level 0, 16-bit Cpu Display Interface Serializer And Deserializer
• Manufacturer: National Semiconductor Corporation

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MPL SERIAL BUS PINS
CONFIGURATION/PARALLEL BUS PINS
CLOCK / POWER DOWN SIGNALS
PARALLEL INTERFACE SIGNALS
Pin Name
INTR/8-bit
CSL*/IDR
Pin Descriptions — CPU
MD[1:0]
D[15:0]
(WR*)
Mode
(RD*)
V
CS1*
CS2*
CPU
M/S*
CLK
MF0
MF1
PD*
A/D
MC
TM
SSA
of Pins
No.
16
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I/O, Type
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
IO, MPL
IO, MPL
Ground
IO,
IO,
IO,
IO,
IO,
IO,
IO,
I,
I,
I,
I,
I,
I,
I,
MPL Data Line Driver/Receiver
MPL Clock Line Driver
MPL Ground - see Power/Ground Pins
CPU mode configuration input
Tie High
Tie High for Master
Test Mode control input
Tie Low for normal mode (High reserved for factory test)
CPU Mode input
Tie High for i80 mode
Local Chip Select input,
Reserved - Tie High.
CLK input
Power Down input,
L = Powered down (sleep mode)
H = active mode
CPU Data Bus inputs / outputs
Multi Function input -
Read input (RD
Multi Function input -
Write input (WR
Chip Select One input
Active Low
Chip Select Two input
Active Low
Address / Data selector input
Interrupt Output
Active High, is asserted when READ
data is ready and de-asserted upon send
READ cycle OPTIONAL
CPU Master
*
*
) for i80 I/F
) for i80 I/F
(MST)
2
Description
MPL Data Receiver/Line Driver
MPL Clock Receiver
Tie Low for Slave
Insert Dummy Read control input,
H = inserts dummy read cycle in all
READ transactions
L = uses one READ cycle for every
READ transaction
NA
CPU Data Bus outputs / inputs
Multi Function output -
Read output (RD
Multi Function output -
Write output (WR
Chip Select One output
Active Low
Chip Select Two output
Active Low
Address / Data selector output
8-bit Mode Input
Tie Low for 16-bit mode
8-bit mode is reserved.
CPU Slave
*
*
(SLV)
) for i80 I/F
) for i80 I/F