aduc847bs8-3 Analog Devices, Inc., aduc847bs8-3 Datasheet - Page 28

• Manufacturer Part Number: aduc847bs8-3
• Description: Microconverter, 10-channel 24-bit Adc With Embedded 62kb Flash Mcu
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
I2CDAT
Function
SFR Address
Power-On Default value
Bit Addressable
SPI SERIAL INTERFACE
The ADuC847 integrates a complete hardware Serial Peripheral
Interface (SPI) interface on-chip. SPI is an industry-standard
synchronous serial interface that allows eight bits of data to be
synchronously transmitted and received simultaneously, i.e., full
duplex. It should be noted that the SPI pins are multiplexed with
Port 2 pins (P2.0, P2.1, P2.2 & P2.3). The pins have SPI
functionality only if SPE is SET. Otherwise, with SPE cleared
standard Port 2 functionality is maintained. SPI can be configured
for master or slave operation and typically consists of four pins,
namely:
SCLOCK (Serial Clock I/O Pin), Pin 28 (MQFP package), Pin 30
(CSP package).
The master clock (sclock) is used to synchronize the data being
transmitted and received through the MOSI and MISO data lines.
A single data bit is transmitted and received in each SCLOCK
period. Therefore, a byte is transmitted/received after eight sclock
periods. The sclock pin is configured as an output in master mode
and as an input in Slave mode. In master mode the bit-rate,
polarity, and phase of the clock are controlled by the CPOL,
CPHA, SPR0, and SPR1 bits in the SPICON SFR (see Table XIII).
In slave mode the SPICON register will have to be configured with
the same phase and polarity (CPHA and CPOL) settings as the
master.
MISO (Master In, Slave Out Pin), Pin 30 (MQFP package), Pin 32
(CSP package).
The MISO (master in slave out) pin is configured as an input line in
Master mode and an output line in Slave mode. The MISO line on
the master (data in) should be connected to the MISO line in the
slave device (data out). The data is transferred as byte-wide (8-bit)
serial data, MSB first.
MOSI (Master Out, Slave In Pin), Pin 29 (MQFP package), Pin31
(CSP package).
The MOSI (master out slave in) pin is configured as an output line
in Master mode and an input line in Slave mode. The MOSI line on
the master (data out) should be connected to the MOSI line in the
slave device (data in). The data is transferred as byte-wide (8-bit)
serial data, MSB first.
SS (Slave Select Input Pin), Pin 31 (MQFP package), Pin 33 (CSP
package).
The Slave Select (SS) input pin is only used when the ADuC847 is
configured in SPI Slave mode. This line is active low. Data is only
received or transmitted in Slave mode when the SS pin is low,
allowing the ADuC847 to be used in single master, multislave SPI
configurations. If CPHA = 1, the SS input may be permanently
pulled low. With CPHA = 0, the SS input must be driven low
before the first bit in a byte wide transmission or reception and
return high again after the last bit in that byte wide transmission or
reception. In SPI Slave mode, the logic level on the external SS pin
REV. PrA 05/03
I
The I2CDAT SFR is written to by user code to transmit data, or read by user code to read data just received by the
I2C interface. Accessing I2CDAT automatically clears any pending I2C interrupt and the I2CI bit in the I2CCON
SFR. User code should only access I2CDAT once per interrupt cycle.
0x9A
0x00
No.
2
C Data Register
28
(Pin 13), can be read via the SPR0 bit in the SPICON SFR. The
following SFR registers are used to control the SPI interface.
ADuC847