hmp8112a Harris Corporation, hmp8112a Datasheet - Page 12

• Manufacturer Part Number: hmp8112a
• Description: Ntsc/pal Video Decoder
• Manufacturer: Harris Corporation

NOTES:
NOTES:
CbCr[7-0]
1. Y
2. ACTIVE is asserted per Figure 13.
3. DVLD is asserted for every valid pixel during both active and blanking regions. DVLD is not a 50% duty cycle synchronous output and will
4. Y
5. ACTIVE stays asserted as soon as 8-Bit mode is selected.
6. DVLD is asserted for every valid pixel during the active region only per Figure 13. DVLD may deassert briefly during the active video region
ACTIVE
ACTIVE
Y[7-0]
Y[7-0]
DVLD
DVLD
CLK
due to the 4:2:2 subsampling. Y
appear to jitter as the Output Sample Rate converter adjusts the output timing for various data rates and clock frequency inputs.
CLK
due to the 4:2:2 subsampling. Pixel data is not output during the blanking period.
as the Output Sample Rate converter adjusts the output timing for various data rates and clock frequency inputs.
0
0
is the first active luminance pixel of a line. Cb
is the first active luminance pixel of a line. Cb
t
NOTE 5
DVLD
Y
Cr
N
N
t
DVLD
N
Cb
the last valid pixel in the blanking period.
0
FIGURE 14. OUTPUT TIMING 16-BIT MODE
FIGURE 15. OUTPUT TIMING 8-BIT MODE
Y
Cb
Y
0
0
NOTE 2
0
0
0
and Cr
and Cr
NOTE 4
NOTE 1
Cr
0
0
0
HMP8112A
NOTE 6
are first active chrominance pixels in a line. Cb and Cr will alternate every cycle
are first active chrominance pixels in a line. Cb and Cr will alternate every cycle
4-12
Y
Cr
Y
1
1
0
NOTE 3
Y
Cb
2
2
Cb
2
Y
Cr
Y
3
2
2
Cr
2
Y
3
Cb
Y
Cb
4
4
4