mc44251 Freescale Semiconductor, Inc, mc44251 Datasheet - Page 6

• Manufacturer Part Number: mc44251
• Description: Triple 8-bit Video Three-state Outputs
• Manufacturer: Freescale Semiconductor, Inc

GENERAL
log–to–digital converters (ADC). Each ADC consists of 256
latching comparators and an encoder. The MC44251 may be
used to convert RGB or YUV video information from an ana-
log to a digital format, or as a triple ADC for non–video in-
formation. For video processing performance enhancement,
each ADC has a dither generator with subsequent digital
correction designed into it. The dithering generator reduces
display degradation from granulation of the luminance
information caused by quantization errors of the digitizing
process. Each ADC is driven from a common clock and
receives common sync information from the HZ and VTN
pins. In addition, the VTN pin controls the dithering function
and disables the dithering generator when VTN is pulled low.
The sampling of the analog input signals occurs at the falling
edge of the clock signal, whereas the digital outputs change
state at the rising clock edge. The bias current of the
comparators is set by an external resistor. Input clamps allow
for ac coupling of the input signals.
CLAMP NETWORK
coupled. When dc coupled, the MC44251 will track the aver-
age dc level of the input waveform. For ac coupling, an
MC44251
6
The MC44251 contains three independent parallel ana-
The MC44251 can be operated either dc coupled or ac
OUT
CLK
IN
(Pin 35)
MODE
Open
H
L
RGB
YUV Mode Without Sync
YUV Mode With Sync
Figure 2. Conversion Timing Functional Characteristics
Application
t d
Table 1. Clamping Levels
CIRCUIT OPERATION
Clamp Levels
Format
on–chip dc restoration circuit samples and adjusts the aver-
age dc level of the input signal. The MC44251 has three
selectable clamping levels for ac coupling. The clamp levels
are selected by the MODE pin according to Table 1. In the
RGB mode, the clamping levels are set to 16/256, corre-
sponding to 6.3% of full range. In the YUV mode, the UV
clamping levels are set to 128/256 (50%) and the Y input to
either 16/256 or 64/256 (25%).
ure 3a, the voltage difference between the analog input volt-
age and the clamp reference voltage is integrated within
each clamp network. At the falling edge of HZ, a latching
comparator senses the sign of the integrator output voltage.
Depending on this result, either a sinking or a sourcing cur-
rent is applied to the analog input pin as long as input HZ re-
mains low.
proper operation of the ADC. The frequency of HZ should be
locked to the line frequency of the video input. The pulse
width and timing of HZ with respect to the video signal is
shown in Figure 4. The top curve represents the horizontal
synchronizing and blanking interval for a video signal. The
pulse width of HZ (t
back porch (t BP ) and coincident with it. In all cases, HZ must
return low before the end of the back porch (t BP ).
When input HZ (horizontal) is high, as illustrated in Fig-
For video applications, the timing of HZ is critical to the
16/256
16/256
64/256
G in
H
128/256
128/256
) should be less than the width of the
16/256
R in
128/256
128/256
16/256
B in
MOTOROLA