sta339bws STMicroelectronics, sta339bws Datasheet - Page 32

• Manufacturer Part Number: sta339bws
• Description: 2.1-channel High-efficiency Digital Audio System
• Manufacturer: STMicroelectronics

Register description
Note:
6.2.4
6.2.5
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happens. At the same time any processing related to the I
only after the serial audio interface and the internal PLL are synchronous again.
Any mute or volume change causes some delay in the completion of the I
to the soft volume feature. The soft volume phase change must be finished before any clock
desynchronization.
Delay serial clock enable
Table 21.
Channel input mapping
Table 22.
Each channel received via I
Channel Input Mapping registers. This allows for flexibility in processing. The default
settings of these registers map each I
channel.
Bit
Bit
5
6
7
R/W
R/W
R/W
R/W
R/W
Delay serial clock enable
Channel input mapping
RST
RST
0
0
1
2
S can be mapped to any internal processing channel via the
DSCKE
Name
Name
C1IM
C2IM
2
S input channel to its corresponding processing
0: Processing channel 1 receives Left I
1: Processing channel 1 receives Right I
0: Processing channel 2 receives Left I
1: Processing channel 2 receives Right I
0: No serial clock delay
1: Serial clock delay by 1 core clock cycle to tolerate
anomalies in some I
2
C configuration should be issued
Description
Description
2
S master devices
2
C operation due
STA339BWS
2
2
S Input
S Input
2
2
S Input
S Input