max2078ctk Maxim Integrated Products, Inc., max2078ctk Datasheet - Page 20

• Manufacturer Part Number: max2078ctk
• Description: Octal-channel Ultrasound Front-end With Cw Doppler Mixers
• Manufacturer: Maxim Integrated Products, Inc.

Octal-Channel Ultrasound Front-End
with CW Doppler Mixers
If drawn, the simplified dominant highpass network
would look like Figure 3.
The highpass pole in this case is at f
~ 5Hz. Note that this low highpass corner frequency is
required to filter the downconverted clutter tone, which
appears at DC, but not interfere with CWD imaging at
frequencies as low as 400Hz. For example, if one want-
ed to use CWD down to 400Hz, then a good choice for
the highpass pole would be at least a decade below
this (< 40Hz) as not to incur rolloff due to the pole.
Remember, if the highpass pole is set to 400Hz, the
response is 3dB down at that corner frequency. The
placement of the highpass pole at 5Hz in the above
example is between the DC and 40Hz limitations just
discussed.
The bottom line is that any reasonably sized DC block
between the output of the mixer and the instrumentation
amplifier poses a significant time constant that slows
the mode select switching speed.
An alternative solution to the approach in Figure 2,
which enables faster mode select response time, is
shown in Figure 4.
In Figure 4, the outputs of the CWD mixers are DC-cou-
pled into the inputs of the instrumentation amplifiers.
Therefore, the op amps must be able to accommodate
the full compliance range of the mixer outputs, which is
a maximum of 11V when the mixers are disabled, down
to the 5V supply of the MAX2078 when the mixers are
enabled. The op amps can be powered from 11V for the
high rail and 5V for the low rail, requiring a 6V op amp.
The MAX2078 is programmed using a serial shift regis-
ter arrangement. This greatly simplifies the complexity
of the program circuitry, reduces the number of IC pins
necessary for programming, and reduces the PCB lay-
out complexity. See Table 5 for the programming bit
order. The data in (DIN) and data out (DOUT) can be
daisy-chained from device to device and all front-ends
can run off a single programming clock.
The data can be entered after CS goes low. Once a
whole word is entered, CS needs to rise. When pro-
gramming the part, enter LSB first and MSB last.
During the normal CWD mode, the mixer clock (LO+,
LO-) is on and the programming signals (DIN, CLK, CS)
are off (CS = high, CLK = low, and DIN = don’t care, but
fixed to a high or a low). To start the programming
sequence, turn off the mixer clock. Data is shifted into
20
______________________________________________________________________________________
Programming the Beamformer
Serial Interface
P
= 1/(2 x pi x RC)
the shift register at a recommended 10MHz program-
ming rate or 100ns minimum data clock period/time.
Assuming a 64-channel CWD receiver, this takes about
30ms for 5 bits per channel. See Figure 5 for timing
details. After the shift registers are programmed, pulling
CS high loads the internal counters into I/Q phase
divider/selectors with the proper values. The mixer clock
needs to be off when this occurs or there may be timing
issues between the load line timing and the mixer clock
timing. The user turns on the mixer clock to start beam-
forming. The clock must turn on so that it starts at the
beginning of a mixer clock cycle. A narrow glitch on the
mixer clock is not acceptable and could cause metasta-
bility in the I/Q phase dividers.
Figure 3. Simplified Circuit of Highpass Pole
Figure 4. Improved Mode Select Response Time Achieved with
DC-Coupled Input to Instrumentation Amplifier
+11V
+5V