lmh6521sqx National Semiconductor Corporation, lmh6521sqx Datasheet - Page 6

• Manufacturer Part Number: lmh6521sqx
• Description: High Performance Dual Dvga
• Manufacturer: National Semiconductor Corporation

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Pin Descriptions
Pin Number
Analog I/O
30, 11
29, 12
24, 17
23, 18
Power
13, 15, 26, 28,
center pad
14, 27
Common Control Pins
4, 5
22, 19
Digital Inputs Parallel Mode (MOD1 = 1, MOD0 = 1)
25, 16
31, 10
32, 9
1, 8
2, 7
3, 6
21, 20
Digital Inputs Serial Mode (MOD1 =1 , MOD0 = 0) SPI compatible
2
1
32
31
3, 4, 6, 7, 8, 9, 10,
16, 20, 21, 25
Digital Inputs Pulse Mode (MOD1 = 0 , MOD0 = 1)
2, 7
1, 8
1 & 2 or 7 & 8
31, 32
10, 9
3, 5, 6, 16, 25
Symbol
INA+, INB+
INA−, INB−
OUTA+, OUTB+
OUTA−, OUTB−
GND
+5V
MOD0, MOD1
ENA, ENB
A0, B0
A1, B1
A2, B2
A3, B3
A4, B4
A5, B5
LATA, LATB
CLK
SDI
CSb
SDO
GND
UPA, UPB
DNA, DNB
S0A, S1A
S0B, S1B
GND
Description
Amplifier non—inverting input. Internally biased to mid supply. Input voltage should not
exceed V+ or go below GND by more than 0.5V.
Amplifier inverting input. Internally biased to mid supply. Input voltage should not exceed
V+ or go below GND by more than 0.5V.
Amplifier non—inverting output. Externally biased to 0V.
Amplifier inverting output. Externally biased to 0V.
Ground pins. Connect to low impedance ground plane. All pin voltages are specified with
respect to the voltage on these pins. The exposed thermal pad is internally bonded to
the ground pins.
Power supply pins. Valid power supply range is 4.75V to 5.25V.
Digital Mode control pins. These pins float to the logic hi state if left unconnected. See
applications section for Mode settings.
Enable pins. Logic 1 = enabled state. See application section for operation in serial mode.
Attenuation bit zero = 0.5dB step. Gain steps down from maximum gain (000000 =
Maximum Gain).
Attenuation bit one = 1dB step.
Attenuation bit two = 2dB step.
Attenuation bit three = 4dB step.
Attenuation bit four = 8dB step.
Attenuation bit five = 16dB step.
Latch pins. Logic zero = active, logic 1 = latched. Gain will not change once latch is high.
Connect to ground if the latch function is not desired.
Serial Clock
Serial Data In. See application section for more details.
Serial Chip Select (Active Low).
Serial Data Out.
Pins unused in Serial Mode, connect to DC ground.
Up pulse pin. A logic 0 pulse will increase gain one step.
Down pulse pin. A logic 0 pulse will decrease gain one step.
Pulsing both pins together will reset the gain to maximum gain.
Step size zero and step size 1. (0,0) = 0.5dB; (0, 1)= 1dB; (1,0) = 2dB, and (1, 1)= 6dB.
Step size zero and step size 1. (0,0) = 0.5dB; (0, 1)= 1dB; (1,0) = 2dB, and (1, 1)= 6dB.
Pins unused in Pulse Mode, connect to DC ground.
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