lmh6514sqx National Semiconductor Corporation, lmh6514sqx Datasheet - Page 5

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lmh6514sqx

Manufacturer Part Number
lmh6514sqx
Description
Lmh6514 600 Mhz, Digital Controlled, Variable Gain Amplifier
Manufacturer
National Semiconductor Corporation
Datasheet
Pin Descriptions
Pin Number
Analog I/O
6
7
15
14
16
13
Power
3
5,8
Digital Inputs
11,10,9
2
1,4,12
Symbol
IN+
IN−
OUT−
OUT+
LOAD−
LOAD+
V
GND
GAIN_0 to
GAIN_2
LATCH
NC
CC
Description
Non-inverting analog input. Internally biased to 1.4V. Input voltage should not exceed
V
Inverting analog input. Internally biased to 1.4V. Input voltage should not exceed V
go below GND by more than 0.5V. If using amplifier single ended this input should be
capacitively coupled to ground.
Open collector inverting output. This pin is an output that also requires a power source.
This pin should be connected to 5V through either an RF choke or an appropriately sized
inductor that can form part of a filter. See application section for details.
Open collector non-inverting output. This pin is an output that also requires a power
source. This pin should be connected to 5V through either an RF choke or an
appropriately sized inductor that can form part of a filter. See application section for
details.
Internal 200Ω resistor connection to pin 15. This pin can be left floating for higher gain
or shorted to pin 13 for lower gain and lower effective output impedance. See application
section for details.
Internal 200Ω resistor connection to pin 14. This pin can be left floating for higher gain
or shorted to pin 16 for lower gain and lower effective output impedance. See application
section for details.
5V power supply pin. Use ceramic, low ESR bypass capacitors. This pin powers
everything except the output stage.
Ground pins. Connect to low impedance ground plane. All pin voltages are specified with
respect to the voltage on these pins. The exposed thermal pad is also a ground
connection.
Gain setting pins. See above table for gain step sizes for each pin. These pins are 3.3V
CMOS logic compatible. 5V inputs may cause damage.
This pin controls the function of the gain setting pins mentioned above. With LATCH in
the logic HIGH state the gain is fixed and will not change. With the LATCH in the logic
LOW state the gain is set by the state of the gain control pins. Any changes in gain made
with the LATCH pin in the LOW state will take effect immediately. This pin is 3.3V CMOS
logic compatible. 5V inputs may cause damage.
These pins are not connected. They can be grounded or left floating.
CC
or go below GND by more than 0.5V.
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