ds8907 National Semiconductor Corporation, ds8907 Datasheet

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ds8907

Manufacturer Part Number
ds8907
Description
Phase-locked Loop Frequency Synthesizer
Manufacturer
National Semiconductor Corporation
Datasheet
C 1995 National Semiconductor Corporation
DS8907 AM FM Digital
Phase-Locked Loop Frequency Synthesizer
General Description
The DS8907 is a PLL synthesizer designed specifically for
use in AM FM radios It contains the reference oscillator a
phase comparator a charge pump a 120 MHz ECL I
dual modulus programmable divider and an 18-bit shift reg-
ister latch for serial data entry The device is designed to
operate with a serial data controller generating the neces-
sary division codes for each frequency and logic state infor-
mation for radio function inputs outputs
The Colpitts reference oscillator for the PLL operates at
4 MHz A chain of dividers is used to generate a 500 kHz
clock signal for the external controller Additional dividers
generate a 25 kHz reference signal for FM and a 10 kHz
reference signal for AM One of these reference signals is
selected by the data from the controller for use by the
phase comparator
Data is transferred between the frequency synthesizer and
the controller via a 3 wire bus system This consists of a
data input line an enable line and a clock line When the
enable line is low data can be shifted from the controller
into the frequency synthesizer When the enable line is tran-
sitioned from low to high data entry is disabled and data
present in the shift register is latched
From the controller 20-bit data stream the first 2 bits ad-
dress the device permitting other devices to share the same
bus Of the remaining 18-bit data word the next 13 bits are
used for the PLL divide code The remaining 5 bits are con-
nected via latches to output pins These 5 bits can be used
to drive radio functions such as gain mute FM AM and
stereo only These outputs are open collector Bit 16 is used
internally to select the AM or FM local oscillator input and to
select between the 10 kHz and 25 kHz reference A high
level at bit 16 indicates FM and a low level indicates AM
The PLL consists of a 13-bit programmable I
ECL phase comparator an ECL dual modulus (p p
scaler and a high speed charge pump The programma-
Connection Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
TL F 7511
2
L divider an
Dual-In-Line Package
a
1) pre-
Top View
2
L
ble divider divides by (N
into the shift register (bits 1 – 13 after address) It is clocked
by the AM input via an ECL
at frequencies up to 15 MHz while the FM input works up to
120 MHz The AM band is tuned with a frequency resolution
of 10 kHz and the FM band is tuned with a resolution of
25 kHz The buffered AM and FM inputs are self biased and
can be driven directly by the VCO through a capacitor The
ECL phase comparator produces very accurate resolution
of the phase difference between the input signal and the
reference oscillator The high speed charge pump consists
of a switchable constant current source (
switchable constant current sink (
quency is low the charge pump will source current and sink
current if the VCO frequency is high When using an AFC
the charge pump output may be forced into TRI-STATE by
applying a low level to the charge pump enable input
A separate V
oscillator and reference chain to provide controller clocking
frequencies when the balance of the PLL is powered down
Features
Y
Y
Y
Y
Y
Y
Y
d
Uses inexpensive 4 MHz reference crystal
F
thesis at FM frequencies
FM resolution of 25 kHz allows usage of 10 7 MHz ce-
ramic filter distribution
Serial data entry for simplified control
50 Hz output for ‘‘time-of-day’’ reference driven from
separate low power V
5-open collector buffered outputs for controlling various
radio functions
Separate AM and FM inputs AM input has 15 mV (typi-
cal) hysteresis
IN
capability greater than 120 MHz allows direct syn-
prescaler from the FM input The AM input will work
CCM
pin (typically drawing 1 5 mA) powers the
TL F 7511 – 1
CCM
a
1) N being the number loaded
d
See NS Package Number
Order Number DS8907N
a
prescaler or through a
0 3 mA) If the VCO fre-
RRD-B30M105 Printed in U S A
b
N20A
0 3 mA) and a
July 1986

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ds8907 Summary of contents

Page 1

... DS8907 AM FM Digital Phase-Locked Loop Frequency Synthesizer General Description The DS8907 is a PLL synthesizer designed specifically for use radios It contains the reference oscillator a phase comparator a charge pump a 120 MHz ECL I dual modulus programmable divider and an 18-bit shift reg- ister latch for serial data entry The device is designed to ...

Page 2

Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (V ) CC1 (V ) CCM Input Voltage Output Voltage DC Electrical Characteristics Symbol Parameter V ...

Page 3

... Note 3 All currents into device pins shown as positive out of device pins as negative all voltages referenced to ground unless otherwise noted All values shown as max or min on absolute value basis Schematic Diagrams (DS8907 AM FM PLL typical Input Output Schematics 7511 – 7511 – 7511 – ...

Page 4

... Timing diagrams are not drawn to scale Scale within any one drawing may not be consistent and intervals are defined positive as drawn SERIAL DATA ENTRY INTO THE DS8907 Serial information entry into the DS8907 is enabled by a low level on the ENABLE input One binary bit is then accepted ...

Page 5

Typical Application Electronically Tuned Radio Controller System Direct Drive LED 7511 – 12 ...

Page 6

Logic Diagram AM FM PLL Synthesizer (Serial Data 20-Pin Package) Sections operating from V supply CCM Address ( 7511 – 13 ...

Page 7

7 ...

Page 8

... National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications Molded Dual-In-Line Package (N) Order Number DS8907N NS Package Number N20A 2 A critical component is any component of a life ...

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