74vcx162839 ETC-unknow, 74vcx162839 Datasheet
74vcx162839
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74vcx162839 Summary of contents
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... OE pin. These devices are ideally suited for buffered or regis- tered 168 pin and 200 pin SDRAM DIMM memory mod- ules. The 74VCX162839 is designed for low voltage (1.65V to 3.6V) V applications with I/O compatibility up to 3.6V. CC The 74VCX162839 is also designed with 26 tors in the outputs ...
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... Z High Impedance LOW-to-HIGH Clock Transition Functional Description The 74VCX162839 consists of twenty selectable non- inverting buffers or registers with word wide modes. Mode functionality is selected through operation of the CLK and REGE pin as shown by the truth table. When REGE is held at a logic HIGH the device operates as a 20-bit register. ...
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Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATE Outputs Active (Note 3) 0. Input Diode Current ( Output ...
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DC Electrical Characteristics (2.3V Symbol Parameter V HIGH Level Input Voltage IH V LOW Level Input Voltage IL V HIGH Level Output Voltage OH V LOW Level Output Voltage OL I Input Leakage Current I I 3-STATE Output Leakage OZ ...
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AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay PHL (REGE 0) PLH t Propagation Delay CLK to O PHL n t (REGE 1) PLH Propagation Delay ...
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AC Loading and Waveforms TEST PLH PHL PZL PLZ PZH PHZ FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage ...
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Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...