tja1082 NXP Semiconductors, tja1082 Datasheet - Page 16

• Manufacturer Part Number: tja1082
• Description: Flexray Node Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
TJA1082_2
Product data sheet
6.8.1 SPI mode
6.8.2 Simple error indication mode
6.9 SPI interface
If a V
and simple error indication mode.
The error flag information in the status register is latched in SPI mode. This means that
the status bit is reset once the status register has been completely read (provided the
corresponding error flag has been reset). If an error condition is detected in Normal mode,
pin ERRN goes LOW (provided one of the error bits, S5-S10, is set). Pin ERRN goes
HIGH again once all the error bits (S5-S10) have been reset.
If an error condition is detected in Normal mode, pin ERRN goes LOW once the relevant
error flag has been set. Pin ERRN goes HIGH again when all error conditions have been
cleared and all flags have been reset. Error flags are not latched. It is not possible to
read-out the status bits in this mode.
The TJA1082 includes a 16-bit SPI interface to enable a host to read the status register
when the transceiver is in SPI mode (see
While pin SCSN is HIGH, the SDO output is in a high-impedance state. To begin a status
register readout, the host must force pin SCSN LOW. This causes the SDO pin to output a
LOW level by default. The data at pin SDO is then shifted out on the rising edge of the
clock signal on pin SCLK.
The status bits shifted out at SDO are active HIGH. The status bits are refreshed and pin
SDO returned to a high-impedance state once the status register has been read
successfully (after exactly 16 clock cycles) and SCSN has been forced HIGH again. Clock
signals on SCLK are ignored while SCSN is HIGH. The timing diagram for the SPI readout
is illustrated in
The SLCK period ranges from 500 ns to 100 s (10 kbit/s to 2 Mbit/s).
Fig 11.
IO
undervoltage condition is detected, it is not possible to switch between SPI mode
Timing diagram for configuration of error indication mode
SCSN
SCLK
(V)
(V)
Figure
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V
IO
IO
0
0
Rev. 02.03 — 10 August 2009
12.
SPI mode
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det(L)(SCLK)
Section
simple error
indication mode
6.8).
FlexRay node transceiver
SPI mode
© NXP B.V. 2009. All rights reserved.
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