mc33742 Freescale Semiconductor, Inc, mc33742 Datasheet - Page 47

• Manufacturer Part Number: mc33742
• Description: Mc33742 System Basis Chip Sbc With Enhanced High-speed Can Transceiver
• Manufacturer: Freescale Semiconductor, Inc

Table 28. Wake-Up Register Control Bits
Table 29. Wake-Up Register Status Bits
TIMING REGISTER (TIM1 / 2)
• TIM1 — Controls the watchdog timing selection as well as either the watchdog window or the watchdog time-out option
• TIM2 — Selects an appropriate timing for sensing the wake-up circuitry or cyclically supplying devices by switching the HS on
Table 30. TIM1 Timing and CANL Failure Diagnostic Register
Analog Integrated Circuit Device Data
Freescale Semiconductor
x = Don’t care.
Notes
Notes
59.
60.
Tables 30
(
described in
or off. TIM2 is selected when bit D3 is 1
Cyclic sense timing characteristics are described in
Both subregisters also report the CANL and TXD diagnostics.
Figure 28
Reset Condition
LCTR3
Reset Value
(Write)
WUR status bits have two functions. After SBC wake-up, they indicate the wake up source; for example, L2WU set at logic [1] if wake-
up source is L2 input. After SBC wake-up and once the WUR register has been read, status bits indicate the real-time state of the Lx
inputs (1 = Lx is above threshold, 0 = Lx input is below threshold). If after a wake-up from Lx input a watchdog tomato occurs before the
first reading of the WUR register, the LxWU bits are reset. This can occur only if the SBC was in Stop mode.
See
0
0
1
1
x
x
x
x
$101b
TIM1
L3WU
L2WU
L1WU
L0WU
Name
Table
and
through
(60)
Table
13, page 42, for definitions of reset conditions.
Figure 29
34
31.
LCTR2
contain the Timing Register information. The TIM register is composed of two sub registers:
0
1
0
1
x
x
x
x
, respectively). TIM1 is selected when bit D3 is 0
R/W
W
R
–
–
Logic
0 or 1
0 or 1
0 or 1
0 or 1
LCTR1
0
0
1
1
x
x
x
x
(Table
CANL2VDD
(59)
D3
0
–
–
32).
Figure
Table
If bit = 1, wake-up occurred from Sleep or Stop modes; if bit = 0, no wake-up has
occurred.
When device is in Normal or Standby mode, bit reports the State on Lx pin (LOW
or HIGH) (0 = Lx LOW, 1 = Lx HIGH)
LCTR0
0
1
0
1
x
x
x
x
30, page 49, describes HS operation when cyclic sense is selected
34, page 49.
POR, RESET
CANL2BAT
WDW
D2
0
L0 L1 : L1 L2 Config
High Level Sensitive
Both Level Sensitive
Low Level Sensitive
(Table
Inputs Disabled
–
30). Watchdog timing characteristics are
Description
POR, RESET
LOGIC COMMANDS AND REGISTERS
CANL2GND
FUNCTIONAL DEVICE OPERATION
WDT1
D1
0
L2 L3 : L3 L4 Config
High Level Sensitive
Both Level Sensitive
Low Level Sensitive
Inputs Disabled
–
POR, RESET
WDT0
TXPD
D0
0
33742
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