xc7318 Xilinx Corp., xc7318 Datasheet - Page 5

• Manufacturer Part Number: xc7318
• Description: Xc7300 Cmos Epld Family ,
• Manufacturer: Xilinx Corp.

Figure 5. High-Density Function Block and Macrocell Schematic
Table 1. Function Generator Logic Operations
Figure 6. ALU Schematic
Products
Products
Sum-of-
Sum-of-
D1
D2
D1:+: D2
D1 * D2
D1 + D2
D1
D1
D1 * D2
D1 + D2
Inputs
Input
from
from
Fast
Pins
Arithmetic Logic Unit (ALU)
UIM
(FI)
21
3
Feedback to UIM
Input to UIM
AND Array
Function Block
P-Terms per
12 Sharable
D1
D2
Macrocells
Carry Control
To 8 More
* OE is forced high when P-term is not used
8
Generator
Function
Arithmetic
Function
from Previous MC
4
to Next MC
P-Terms per
Shift-Out
Macrocell
5 Private
Shift-In
Carry Input
D1:+: D2
D1 * D2
D1 + D2
D2
D2
D1 * D2
D1 + D2
0
1
Carry Output
5
To Macrocell
Flip-Flop
Arithmetic Carry-In from
Feedback
Local
Previous Macrocell
X3206
CLOCK
RESET
Carry-Out to Next
2-5
OE*
SET
Arithmetic
Macrocell
D1
D2
C
Therefore, the ALU can implement one additional layer
of logic without any speed penalty.
In arithmetic mode, the ALU block can be programmed to
generate the arithmetic sum or difference of the D1 and
D2 inputs. Combined with the carry input from the next
lower Macrocell, the ALU operates as a 1-bit full adder
generating a carry output to the next higher Macrocell.
The carry chain propagates between adjacent Macrocells
and also crosses the boundaries between Function
Blocks. This dedicated carry chain overcomes the inher-
ent speed and density problems of the traditional EPLD
architecture when trying to perform arithmetic functions.
Carry Lookahead
Each Function Block provides a carry lookahead genera-
tor capable of anticipating the carry across all nine Mac-
rocells. The carry lookahead generator reduces the
ripple-carry delay of wide arithmetic functions such as
add, subtract, and magnitude compare to that of the first
nine bits, plus the carry lookahead delay of the higher-
order Function Blocks.
Macrocell Flip-Flop
The ALU block output drives the input of a programmable
D-type flip-flop. The flip-flop is triggered by the rising edge
of the clock input, but it can be configured as transparent,
C
out
in
ALU
F
Clocks
Fast
0 1
Select
Clock
D
1 of 9 Macrocells
R S
Feedback
Polarity
Q
Trasparent
Register
Control
Register/Latch
Feedback
Enable
Override
Fast OE
Input-Pad
(optional)
Global
OE Control
(see fig.7)
I/O
X5485
Pin