palce20ra10 Lattice Semiconductor Corp., palce20ra10 Datasheet - Page 13

• Manufacturer Part Number: palce20ra10
• Description: 24-pin Asynchronous Ee Cmos Programmable Array Logic
• Manufacturer: Lattice Semiconductor Corp.

POWER-UP RESET
The PALCE20RA10 has been designed with the capa-
bility to reset during system power-up. Following power-
up, all flip-flops will be reset to LOW. The output state
will be HIGH independent of the logic polarity. This fea-
ture provides extra flexibility to the designer and is espe-
cially valuable in simplifying state machine initialization.
A timing diagram and parameter table are shown below.
Due to the synchronous operation of the power-up reset
OUTPUT REGISTER PRELOAD
The preload function allows the register to be loaded
from the output pins. This feature aids functional testing
of sequential designs by allowing direct setting of output
states. The procedure for preloading follows.
1. Disable output registers.
2. Apply either VIH or VIL to all registered outputs.
3. Pulse PL from VIH to VIL to VIH.
4. Remove VIL/VIH from all registered output pins.
2-196
Parameter
Symbol
Leave combinatorial outputs floating.
Disable/Enable
t
t
WL
PR
t
S
Registered
Register
Output
Outputs
Power
Clock
Preload
Output
Clock
Pin 1
Parameter Descriptions
Power-Up Reset Time
Input or Feedback Setup Time
Clock Width LOW
4 V
Output Register Preload Waveform
t
ER
Power-Up Reset Waveform
PALCE20RA10 Family
t
WL
t
PR
t
S
and the wide range of ways V
state, two conditions are required to ensure a valid
power-up reset. These conditions are:
5. Enable the output registers.
6. Verify VOL/VOH at all registered output pins. Note
The V
Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
that because of the output inverter, a register that
has been preloaded HIGH will provide a LOW at
the output. Also note that because there is an in-
verter on the register preload input, the level pre-
sented on the register preload input at the time of
preload will be present on the register output pin
following the preload sequence e.g., a low on the
register pin at the time of preload will result in a
low on that pin after preload.
t
HP
t
WL
CC
t
S
rise must be monotonic.
t
EA
See Switching Characteristics
1000
Max
CC
15434H-19
can rise to its steady
15434H-18
V
CC
Unit
ns