omap1510 ETC-unknow, omap1510 Datasheet - Page 3

• Manufacturer Part Number: omap1510
• Description: Application Processor For 2.5 And 3g Wireless Devices
• Manufacturer: ETC-unknow

ing a large memory space for
power efficient on-chip data and
code storage for applications such
as liquid crystal display (LCD)
frame buffering. A two level inter-
rupt handler provides 32 inter-
rupt lines including 13 internal
and 19 external interrupts. Also
included in the core is the ARM
CP15 coprocessor and protection
module.
DSP Advantage
The 200 MHz C55x DSP core sets
the DSP industry’s benchmark
power and performance ratio.
Three key innovations enable
this: increased idle domains,
variable length instructions and
increased parallelism. The C55x
DSP core has a highly optimized
architecture for multimedia
applications, including core level
extensions that facilitate the
demands of the multimedia mar-
ket for real-time, low-power pro-
cessing of streaming video and
audio. The C55x DSP core con-
tains three multimedia extensions
to further improve the power
efficiency. These are motion esti-
mation, discrete cosine transform
(DCT), inverse discrete cosine
transform (IDCT) and 1/2- pixel
interpolation. The addition of
this hardware accelerator enables
video applications to run up to
twice as fast while also reducing
the power consumption.
32 kwords of internal dual-access
SRAM, 48 kwords of internal
single access SRAM and a
12 kword instruction cache. The
C55x DSP core also includes an
MMU as well as a dual layer inter-
rupt handler and a direct memory
access (DMA) unit. The DMA
allows the transfer of data
between points in the memory
The C55x DSP core includes
space as well as between periph-
erals without Microprocessor Unit
(MPU) intervention.
LCD Controller
The LCD controller allows a
direct connection to a black and
white or color LCD panel, either
super twist nematic (STN) or thin
film transistor (TFT), reducing
the system component count and
power consumption. The frame
buffer can be allocated in external
SDRAM or internal 1.5Mb SRAM
for improved power efficiency. A
dedicated channel on the DMA
unit is used to transfer data from
the frame buffer to the LCD con-
troller. The LCD controller can
support 2/4/8/12/16-bits per pixel
and a 1024x1024 display.
Memory Interfaces
The OMAP1510 processor con-
tains three memory interfaces–
two external and one internal.
The external memory interfaces
support direct connection to
64MB of addressable SDRAM up
to 100 MHz and to 32MB of
addressable Flash (asynchronous
or burst), random access memory
(RAM) or read only memory
(ROM) devices. Both of these
external memory interfaces are
16-bits data wide and support
external devices having 2.75-V or
1.8-V (typical) interfaces. The
internal memory port connects to
the 1.5 Mb of on-chip SRAM. All
three memory interfaces are
accessible and can be shared by
the TI-enhanced ARM 925 MPU,
C55x DSP core and system DMA.
The system DMA is included to
allow transfers of data between
points in the memory space
without MPU intervention. Data
movements to and from internal
memory, external memory and
3
peripherals can occur in the
background of MPU operation.
Camera Interface
Video applications will be an
important part of next-generation
wireless appliances. A camera
interface allows the OMAP1510
to connect directly with a camera
module for video conferencing
and other video applications.
The interface uses 8-bit parallel
image data, pixel clock and
horizontal/vertical sync signals for
the interface. Additionally, a clock
can be provided to the external
camera at various configurable
frequencies. The pixel clock can
be synchronous or asynchronous
depending on the requirements
of the external camera module.
A DMA port allows camera data
to be transferred without the
need for MPU intervention.
Air Interface
An external modem device
can be connected directly to the
OMAP1510 through a modem
interface, allowing both data and
voice communications. The inter-
face has been designed to work
with any air interface standard,
making it easy to use in any
system. The data is transferred on
the TI standard Multi-channel
Buffered Serial Port (McBSP) at
configurable rates up to 6 Mbps
while the control is done through
a UART along with control signal
lines for the clock and power. The
8-kHz voice data can be trans-
ferred by the Multi-Channel Serial
Interface (MCSI). The McBSP
and universal asynchronous
receiver transmitter (UART) have
DMA support, reducing the MPU
loading.