ksz8041tl-ftl Micrel Semiconductor, ksz8041tl-ftl Datasheet - Page 15

• Manufacturer Part Number: ksz8041tl-ftl
• Description: 10base-t/100base-tx/100base-fx Physical Layer Transceiver
• Manufacturer: Micrel Semiconductor

Micrel, Inc.
Strapping Options
April 2007
(KSZ8041FTL)
(KSZ8041TL)
Pin Number
22
21
20
27
41
40
29
43
43
Pin Name
CONFIG2
CONFIG1
CONFIG0
PHYAD2
PHYAD1
PHYAD0
SPEED /
SPEED
no FEF
ISO
Type
Ipd/O
Ipd/O
Ipu/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipu/O
Ipu/O
(1)
Pin Function
The PHY Address is latched at power-up / reset and is configurable to any value from
1 to 7.
The default PHY Address is 00001.
PHY Address bits [4:3] are always set to ‘00’.
The CONFIG[2:0] strap-in pins are latched at power-up / reset and are defined as
follows:
ISOLATE mode
During power-up / reset, this pin value is latched into register 0h bit 10.
SPEED mode
During power-up / reset, this pin value is latched into register 0h bit 13 as the Speed
Select, and also is latched into register 4h (Auto-Negotiation Advertisement) as the
Speed capability support.
If copper mode (FXEN=0), pin strap-in is SPEED mode.
During power-up / reset, this pin value is latched into register 0h bit 13 as the Speed
Select, and also is latched into register 4h (Auto-Negotiation Advertisement) as the
Speed capability support.
If fiber mode (FXEN=1), pin strap-in is no FEF.
This pin value is latched during power-up / reset.
CONFIG[2:0]
000
001
010
011
100
101
110
111
Pull-up = Enable
Pull-down (default) = Disable
Pull-up (default) = 100Mbps
Pull-down = 10Mbps
Pull-up (default) = 100Mbps
Pull-down = 10Mbps
Pull-up (default) = Enable Far-End Fault
Pull-down = Disable Far-End Fault
Mode
MII (default)
RMII
SMII
Reserved – not used
PCS Loopback
RMII back-to-back
MII back-to-back
Reserved – not used
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M9999-042707-1.1
KSZ8041TL/FTL