ade7756arsrl Analog Devices, Inc., ade7756arsrl Datasheet - Page 5

• Manufacturer Part Number: ade7756arsrl
• Description: Active Energy Metering Ic With Serial Interface
• Manufacturer: Analog Devices, Inc.

TIMING CHARACTERISTICS
Parameter
Write Timing
Read Timing
NOTES
1
2
3
4
Specifications subject to change without notice.
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to
90%) and timed from a voltage level of 1.6 V.
See timing diagram below and Serial Interface section of this data sheet.
Measured with the load circuit in Load Circuit for Timing Specifications and defined as the time required for the output to cross 0.8 V or 2.4 V.
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Load Circuit for Timing Specifications. The measured
number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics
is the true bus relinquish time of the part and is independent of the bus loading.
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
10
11
12
13
3
4
4
SCLK
DOUT
SCLK
A, B Versions
20
150
150
10
5
6.4
4
100
4
4
30
100
10
100
10
DIN
DIN
CS
CS
t
t
1
1
1
0
t
2
0
0
Unit
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
µs (min)
µs (min)
ns (min)
µs (min)
µs (min)
ns (min)
ns (max)
ns (min)
ns (max)
ns (min)
COMMAND BYTE
COMMAND BYTE
0
0
1, 2
t
A4
A4
4
t
(AV
XTAL, T
3
A3
A3
DD
OUTPUT
= DV
A2
A2
MIN
t
5
Test Conditions/Comments
CS falling edge to first SCLK falling edge.
SCLK logic high pulsewidth.
SCLK logic low pulsewidth.
Valid Data Setup time before falling edge of SCLK.
Data Hold time after SCLK falling edge.
Minimum time between the end of data byte transfers.
Minimum time between byte transfers during a serial write.
CS Hold time after SCLK falling edge.
Minimum time between read command (i.e., a write to Communication
Register) and data read.
Minimum time between data byte transfers during a multibyte read.
Data access time after SCLK rising edge following a write to the
Communications Register.
Bus relinquish time after falling edge of SCLK.
Bus relinquish time after rising edge of CS.
PIN
TO
to T
DD
A1
A1
= 5 V
MAX
50pF
A0
A0
C
L
= –40 C to +85 C, unless otherwise noted.)
t
t
11
200 A
9
1.6mA
5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz
MOST SIGNIFICANT BYTE
MOST SIGNIFICANT BYTE
DB7
DB7
I
I
OL
OH
2.1V
t
11
DB0
DB0
t
t
10
7
LEAST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
DB7
DB7
t
6
t
12
DB0
DB0
t
13
t
8
ADE7756