at6010a-4qi ATMEL Corporation, at6010a-4qi Datasheet

at6010a-4qi

Manufacturer Part Number

at6010a-4qi

Description

Coprocessor Field Programmable Gate Arrays

Manufacturer

ATMEL Corporation

Datasheet

1.AT6010A-4QI.pdf (28 pages)

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Features

•

Description

AT6000 Series SRAM-based Field Programmable Gate Arrays (FPGAs) are ideal for

use as reconfigurable coprocessors and implementing compute-intensive logic.

Supporting system speeds greater than 100 MHz and using a typical operating current

of 15 to 170 mA, AT6000 Series devices are ideal for high-speed, compute-intensive

designs. These FPGAs are designed to implement Cache Logic

user with the ability to implement adaptive hardware and perform hardware

acceleration.

The patented AT6000 Series architecture employs a symmetrical grid of small yet

powerful cells connected to a flexible busing network. Independently controlled clocks

and resets govern every column of cells. The array is surrounded by programmable

I/O.

AT6000 Series Field Programmable Gate Arrays

Device

Usable Gates

Cells

Registers (maximum)

I/O (maximum)

Typ. Operating Current (mA)

Cell Rows x Columns

High-performance

Up to 204 User I/Os

Thousands of Registers

Cache Logic

Low Voltage and Standard Voltage Operation

Automatic Component Generators

Very Low-power Consumption

Programmable Clock Options

Independently Configurable I/O (PCI Compatible)

Easy Migration to Atmel Gate Arrays for High Volume Production

– System Speeds > 100 MHz

– Flip-flop Toggle Rates > 250 MHz

– 1.2 ns/1.5 ns Input Delay

– 3.0 ns/6.0 ns Output Delay

– Complete/Partial In-System Reconfiguration

– No Loss of Data or Machine State

– Adaptive Hardware

– 5.0 (V

– 3.3 (V

– Reusable Custom Hard Macro Functions

– Standby Current of 500 µA/ 200 µA

– Typical Operating Current of 15 to 170 mA

– Independently Controlled Column Clocks

– Independently Controlled Column Resets

– Clock Skew Less Than 1 ns Across Chip

– TTL/CMOS Input Thresholds

– Open Collector/Tristate Outputs

– Programmable Slew-rate Control

– I/O Drive of 16 mA (combinable to 64 mA)

= 4.75V to 5.25V)

= 3.0V to 3.6V)

Design

AT6002

32 x 32

15 - 30

6,000

1,024

AT6003

40 x 40

25 - 45

1,600

9,000

1,600

120

AT6005

56 x 56

40 - 80

15,000

3,136

108

, which provides the

(continued)

85 - 170

AT6010

80 x 80

30,000

6,400

204

Coprocessor

Field

Programmable

Gate Arrays

AT6000(LV)

Series

Rev. 0264F–10/99

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at6010a-4qi Summary of contents

Page 1

Features • High-performance – System Speeds > 100 MHz – Flip-flop Toggle Rates > 250 MHz – 1.2 ns/1.5 ns Input Delay – 3.0 ns/6.0 ns Output Delay • 204 User I/Os • Thousands of Registers ® • ...

Devices range in size from 4,000 to 30,000 usable gates, and 1024 to 6400 registers. Pin locations are consistent throughout the AT6000 Series for easy design migration. High-I/O versions are available for the lower gate count devices. AT6000 Series FPGAs ...

Page 3

Figure 2. Busing Network (one sector) Figure 3. Cell-to-cell and Bus-to-bus Connections AT6000(LV) Series CELL REPEATER 3 ...

Page 4

Each cell, in addition, provides the ability to route a signal turn between the NS1 bus and EW1 bus and between the NS2 bus and EW2 bus. Express buses are not connected directly to cells, and thus ...

Page 5

In addition to the four local-bus connections, a cell receives two inputs and provides two outputs to each of its North (N), South (S), East (E) and West (W) neighbors. These inputs and outputs are divided into two classes: “A” ...

Page 6

Figure 5. Combinatorial Physical States ...

Page 7

Clock Distribution Along the top edge of the array is logic for distributing clock signals to the D flip-flop in each logic cell (Figure 10). The distribution network is organized by column and permits columns of cells to be independently ...

Page 8

Figure 11. A-type I/O Logic Figure 12. B-type I/O Logic TTL/CMOS Inputs A user-configurable bit determines the threshold level – TTL or CMOS – of the input buffer. Open Collector/Tristate Outputs A user-configurable bit which enables or disables the active ...

Page 9

The devices can be partially reconfigured while in opera- tion. Portions of the device not being modified remain operational during reconfiguration. Simultaneous configu- ration of more than one device is also possible. Full configuration takes as little as a millisecond, ...

Page 10

FPGA. Addresses change after the rising edge of the CCLK signal. CSOUT or I/O When cascading devices, CSOUT is an output used to enable other devices. CSOUT should be connected to the CS input of the ...

Page 11

Pinout Assignment AT6002 AT6003 AT6005 - - - I/O24( I/O30( I/O27( I/O29( I/O28(A) I/O26(A) I/O23( I/O27(A) or ...

Page 12

Pinout Assignment (Continued) AT6002 AT6003 AT6005 I/O9(B) I/O11(B) I/O10( I/O8( I/O10( I/O9( I/O7(B) I/O9(B) I/O8( I/O6( I/O8( I/O7( ...

Page 13

Pinout Assignment AT6002 AT6003 AT6005 CON CON CON - - - I/O96(A) I/O120(A) I/O108(A) - I/O119( I/O118(A) I/O107(A) I/O95(A) or I/O117(A) or I/O106(A) or CSOUT CSOUT ...

Page 14

Pinout Assignment (Continued) AT6002 AT6003 AT6005 - - - VCC VCC VCC I/O82(A) I/O102(A) I/O92(A) I/O81(B) I/O101(B) I/O91( I/O80(A) I/O100(A) I/O90(A) I/O79(B) I/O99(B) I/O89( I/O78(A) I/O98(A) I/O88(A) - I/O97(B) I/O87(A) - ...

Page 15

Pinout Assignment AT6002 AT6003 AT6005 - - - I/O72(A) I/O90(A) I/O81(A) - I/O89(B) I/O80( I/O88(A) - I/O71(A) I/O87(A) I/O79( I/O70(B) I/O86(A) ...

Page 16

Pinout Assignment (Continued) AT6002 AT6003 AT6005 I/O57(B) I/O71(B) I/O64( I/O56(A) I/O70(A) I/O63(A) I/O55(B) I/O69(B) I/O62( I/O54(A) I/O68(A) I/O61(A) - I/O67(B) I/O60( GND GND GND - - - - ...

Page 17

Pinout Assignment AT6002 AT6003 AT6005 I/O48(A) I/O60(A) I/O54(A) - I/O59( I/O58(A) I/O53(A) I/O47(A) I/O57(A) I/O52( ...

Page 18

Pinout Assignment (Continued) AT6002 AT6003 AT6005 I/O34(A) or A13 I/O42(A) or A13 I/O38(A) or A13 I/O33(B) I/O41(B) I/O37( I/O32(A) or A12 I/O40(A) or A12 I/O36(A) or A12 I/O31(B) I/O39(B) I/O35( I/O30(A) ...

Page 19

AC Timing Characteristics – 5V Operation Delays are based on fixed load. Loads for each type of device are described in the notes. Delays are in nanoseconds. Worst case 4.75V to 5.25V. Temperature = ...

Page 20

AC Timing Characteristics – 3.3V Operation Delays are based on fixed load. Loads for each type of device are described in the notes. Delays are in nanoseconds. Worst case 3.0V to 3.6V. Temperature = ...

Page 21

Absolute Maximum Ratings* Supply Voltage (V ) ........................................-0. 7. Input Voltage (V ) ...............................-0. Output Voltage (V ) ...........................-0. Storage Temperature Range (TSTG)........................................................... -65°C to +150°C Power Dissipation (PD)............................................. ...

Page 22

DC Characteristics – 5V Operation Symbol Parameter V High-level Input Voltage IH V Low-level Input Voltage IL V High-level Output Voltage OH V Low-level Output Voltage OL High-level Tristate I OZH Output Leakage Current High-level Tristate I OZL Output Leakage ...

Page 23

DC Characteristics – 3.3V Operation Symbol Parameter V High-level Input Voltage IH V Low-level Input Voltage IL V High-level Output Voltage OH V Low-level Output Voltage OL High-level Tristate I OZH Output Leakage Current High-level Tristate I OZL Output Leakage ...

Page 24

Ordering Information – AT6002 Usable Speed Gates Grade (ns) Ordering Code 6,000 2 AT6002-2AC AT6002A-2AC AT6002-2JC AT6002-2QC AT6002-2AI AT6002A-2AI AT6002-2JI AT6002-2QI 6,000 4 AT6002-4AC AT6002A-4AC AT6002-4JC AT6002-4QC AT6002LV-4AC AT6002ALV-4AC AT6002LV-4JC AT6002LV-4QC AT6002-4AI AT6002A-4AI AT6002-4JI AT6002-4QI 84J 84-lead, Plastic J-leaded Chip ...

Page 25

Ordering Information – AT6003 Usable Speed Gates Grade (ns) Ordering Code 9,000 2 AT6003-2AC AT6003A-2AC AT6003-2JC AT6003-2QC AT6003-2AI AT6003A-2AI AT6003-2JI AT6003-2QI 9,000 4 AT6003-4AC AT6003A-4AC AT6003-4JC AT6003-4QC AT6003LV-4AC AT6003ALV-4AC AT6003LV-4JC AT6003LV-4QC AT6003-4AI AT6003A-4AI AT6003-4JI AT6003-4QI 84J 84-lead, Plastic J-leaded Chip ...

Page 26

Ordering Information – AT6005 Usable Speed Gates Grade (ns) Ordering Code 15,000 2 AT6005-2AC AT6005A-2AC AT6005-2JC AT6005-2QC AT6005A-2QC AT6005-2AI AT6005A-2AI AT6005-2JI AT6005-2QI AT6005A-2QI 15,000 4 AT6005-4AC AT6005A-4AC AT6005-4JC AT6005-4QC AT6005A-4QC AT6005LV-4AC AT6005ALV-4AC AT6005LV-4JC AT6005LV-4QC AT6005ALV-4QC AT6005-4AI AT6005A-4AI AT6005-4JI AT6005-4QI AT6005A-4QI ...

Page 27

... AT6010H-4QC AT6010ALV-4AC AT6010LV-4QC AT6010LV-4JC AT6010ALV-4QC AT6010HLV-4QC AT6010A-4AI AT6010-4QI AT6010-4JI AT6010A-4QI AT6010H-4QI 84J 84-lead, Plastic J-leaded Chip Carrier (PLCC) 100A 100-lead, Very Thin (1.0 mm) Plastic Gull-Wing Quad Flat Package (VQFP) 132Q 132-lead, Bumpered Plastic Gull-Wing Quad Flat Package (BQFP) 144A 144-lead, Thin (1.4 mm) Plastic Gull-Wing Quad Flat Package (TQFP) ...

Page 28

... Atmel Corporation 1999. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war- ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...

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